A reconfigurable fractional interpolation hardware for VVC motion compensation

Hasan Azgin; Ahmet Can Mert; Ercan Kalali; Ilker Hamzaoglu

doi:10.1109/DSD.2018.00030

A reconfigurable fractional interpolation hardware for VVC motion compensation

Hasan Azgin, Ahmet Can Mert, Ercan Kalali, Ilker Hamzaoglu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

20 Citations (Scopus)

Abstract

Fractional interpolation is one of the most computationally complex parts of video compression standards. Fractional interpolation in Versatile Video Coding (VVC) standard has much higher computational complexity than fractional interpolation in previous video compression standards. In this paper, a reconfigurable VVC fractional interpolation hardware for motion compensation is designed and implemented using Verilog HDL. The proposed hardware is the first VVC fractional interpolation hardware for motion compensation in the literature. It interpolates necessary fractional pixels for 1/16 pixel accuracy for all prediction unit sizes. The proposed VVC fractional interpolation hardware, in the worst case, can process 66 quad full HD (3840x2160) frames per second. It has up to 77% less power consumption than baseline VVC fractional interpolation hardware.

Original language	English
Title of host publication	2018 21st Euromicro Conference on Digital System Design (DSD)
Publisher	Institute of Electrical and Electronics Engineers
Pages	99-103
Number of pages	5
ISBN (Electronic)	978-1-5386-7377-5
DOIs	https://doi.org/10.1109/DSD.2018.00030
Publication status	Published - 15 Oct 2018
Externally published	Yes
Event	21st Euromicro Conference on Digital System Design, DSD 2018 - Prague, Czech Republic Duration: 29 Aug 2018 → 31 Aug 2018 Conference number: 21 http://dsd-seaa2018.fit.cvut.cz/dsd/

Conference

Conference	21st Euromicro Conference on Digital System Design, DSD 2018
Abbreviated title	DSD 2018
Country/Territory	Czech Republic
City	Prague
Period	29/08/18 → 31/08/18
Internet address	http://dsd-seaa2018.fit.cvut.cz/dsd/

Keywords

VVC
Motion compensation
Fractional Interpolation
FPGA
Hardware Implementation

Access to Document

10.1109/DSD.2018.00030

Cite this

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title = "A reconfigurable fractional interpolation hardware for VVC motion compensation",

abstract = "Fractional interpolation is one of the most computationally complex parts of video compression standards. Fractional interpolation in Versatile Video Coding (VVC) standard has much higher computational complexity than fractional interpolation in previous video compression standards. In this paper, a reconfigurable VVC fractional interpolation hardware for motion compensation is designed and implemented using Verilog HDL. The proposed hardware is the first VVC fractional interpolation hardware for motion compensation in the literature. It interpolates necessary fractional pixels for 1/16 pixel accuracy for all prediction unit sizes. The proposed VVC fractional interpolation hardware, in the worst case, can process 66 quad full HD (3840x2160) frames per second. It has up to 77% less power consumption than baseline VVC fractional interpolation hardware.",

keywords = "VVC, Motion compensation, Fractional Interpolation, FPGA, Hardware Implementation",

author = "Hasan Azgin and Mert, {Ahmet Can} and Ercan Kalali and Ilker Hamzaoglu",

note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 21st Euromicro Conference on Digital System Design, DSD 2018, DSD 2018 ; Conference date: 29-08-2018 Through 31-08-2018",

year = "2018",

month = oct,

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doi = "10.1109/DSD.2018.00030",

language = "English",

pages = "99--103",

booktitle = "2018 21st Euromicro Conference on Digital System Design (DSD)",

publisher = "Institute of Electrical and Electronics Engineers",

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}

Azgin, H, Mert, AC, Kalali, E & Hamzaoglu, I 2018, A reconfigurable fractional interpolation hardware for VVC motion compensation. in 2018 21st Euromicro Conference on Digital System Design (DSD)., 8491801, Institute of Electrical and Electronics Engineers, pp. 99-103, 21st Euromicro Conference on Digital System Design, DSD 2018, Prague, Czech Republic, 29/08/18. https://doi.org/10.1109/DSD.2018.00030

A reconfigurable fractional interpolation hardware for VVC motion compensation. / Azgin, Hasan; Mert, Ahmet Can; Kalali, Ercan et al.
2018 21st Euromicro Conference on Digital System Design (DSD). Institute of Electrical and Electronics Engineers, 2018. p. 99-103 8491801.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A reconfigurable fractional interpolation hardware for VVC motion compensation

AU - Azgin, Hasan

AU - Mert, Ahmet Can

AU - Kalali, Ercan

AU - Hamzaoglu, Ilker

N1 - Conference code: 21

PY - 2018/10/15

Y1 - 2018/10/15

N2 - Fractional interpolation is one of the most computationally complex parts of video compression standards. Fractional interpolation in Versatile Video Coding (VVC) standard has much higher computational complexity than fractional interpolation in previous video compression standards. In this paper, a reconfigurable VVC fractional interpolation hardware for motion compensation is designed and implemented using Verilog HDL. The proposed hardware is the first VVC fractional interpolation hardware for motion compensation in the literature. It interpolates necessary fractional pixels for 1/16 pixel accuracy for all prediction unit sizes. The proposed VVC fractional interpolation hardware, in the worst case, can process 66 quad full HD (3840x2160) frames per second. It has up to 77% less power consumption than baseline VVC fractional interpolation hardware.

AB - Fractional interpolation is one of the most computationally complex parts of video compression standards. Fractional interpolation in Versatile Video Coding (VVC) standard has much higher computational complexity than fractional interpolation in previous video compression standards. In this paper, a reconfigurable VVC fractional interpolation hardware for motion compensation is designed and implemented using Verilog HDL. The proposed hardware is the first VVC fractional interpolation hardware for motion compensation in the literature. It interpolates necessary fractional pixels for 1/16 pixel accuracy for all prediction unit sizes. The proposed VVC fractional interpolation hardware, in the worst case, can process 66 quad full HD (3840x2160) frames per second. It has up to 77% less power consumption than baseline VVC fractional interpolation hardware.

KW - VVC

KW - Motion compensation

KW - Fractional Interpolation

KW - FPGA

KW - Hardware Implementation

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M3 - Conference contribution

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A reconfigurable fractional interpolation hardware for VVC motion compensation

Abstract

Conference

Keywords

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