Abstract
We define a protocol for on-chip communication that supports dynamic interconnect networks with global memory management based on the notion of distributed shared memory with a uniform address space. The protocol is implemented by a memory manager. It is beneficial to separate the steady-state processing (data communication with static interconnect) from changing from one steady state (or user function) to another, which may necessitate reallocation of resources or changes in the network topology.
| Original language | English |
|---|---|
| Title of host publication | IEEE International Symposium on Circuits and Systems (ISCAS 2001), 6 May 2001 through 9 May 2001, Sydney, NSW |
| Place of Publication | Piscataway |
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 225-228 |
| Number of pages | 4 |
| Volume | 2 |
| ISBN (Print) | 0-7803-6685-9 |
| DOIs | |
| Publication status | Published - 2001 |
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