A power-optimal design methodology for high-resolution low-bandwidth SC ΔΣ Modulators

In this paper, a methodology for the power-optimal design of high-resolution low-bandwidth switched-capacitor $DeltaSigma$ modulators ($ DeltaSigmahbox{Ms}$) is presented. The most power-efficient $ DeltaSigma$ architecture is identified among single-loop feedback and feedforward topologies with different loop orders $N$, oversampling ratios $OSR$, and quantizer resolutions $B$. Based on this study, an experimental prototype has been implemented in a 0.18- $muhbox{m}$ CMOS process. It achieves a signal-to-noise ratio of 95 dB over a signal bandwidth $f_{rm BW}$ of 10 kHz. The prototype operates with a 1.28-MHz sampling rate and consumes 210 $muhbox{W}$ from a 1.8-V supply.