A PLL Frequency Synthesizer in 65 nm CMOS for 60 GHz Sliding-IF Transceiver

Yang Liu, Zhiqun Li, Hao Gao

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

This paper presents an integer Phase-Locked Loop chip for 802.15.3c sliding-IF transceiver. The PLL is composed of a voltage-controlled oscillator, a current-mode logic divide-by-2, a programmable frequency divider, a phase/frequency detector, a charge pump, and an on-chip loop filter. The proposed PLL chip is fabricated using a 65 nm CMOS process, and the chip size is 1.27 mm2. The locking range of the proposed PLL is 23.328 25.92 GHz, the measured phase noise is-98.8 dBc/Hz@1 MHz, reference spur is-62.4 dBc. The power consumption of the PLL is 45.6 mW including the output buffer.

Original languageEnglish
Title of host publication2020 15th European Microwave Integrated Circuits Conference (EuMIC)
PublisherInstitute of Electrical and Electronics Engineers
Pages221-224
Number of pages4
ISBN (Electronic)9782874870606
Publication statusPublished - 10 Jan 2021
Event15th European Microwave Integrated Circuits Conference (EuMIC 2020) - Utrecht, Netherlands
Duration: 11 Jan 202115 Jan 2021
Conference number: 15

Conference

Conference15th European Microwave Integrated Circuits Conference (EuMIC 2020)
Abbreviated titleEuMIC 2020
Country/TerritoryNetherlands
CityUtrecht
Period11/01/2115/01/21

Keywords

  • 65nm CMOS
  • CML frequency divider
  • phase-locked loop
  • voltage-controlled oscillator

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