A PLL Frequency Synthesizer in 65 nm CMOS for 60 GHz Sliding-IF Transceiver

Yang Liu; Zhiqun Li; Hao Gao

A PLL Frequency Synthesizer in 65 nm CMOS for 60 GHz Sliding-IF Transceiver

Yang Liu, Zhiqun Li, Hao Gao

Integrated Circuits

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

This paper presents an integer Phase-Locked Loop chip for 802.15.3c sliding-IF transceiver. The PLL is composed of a voltage-controlled oscillator, a current-mode logic divide-by-2, a programmable frequency divider, a phase/frequency detector, a charge pump, and an on-chip loop filter. The proposed PLL chip is fabricated using a 65 nm CMOS process, and the chip size is 1.27 mm2. The locking range of the proposed PLL is 23.328 25.92 GHz, the measured phase noise is-98.8 dBc/Hz@1 MHz, reference spur is-62.4 dBc. The power consumption of the PLL is 45.6 mW including the output buffer.

Original language	English
Title of host publication	2020 15th European Microwave Integrated Circuits Conference (EuMIC)
Publisher	Institute of Electrical and Electronics Engineers
Pages	221-224
Number of pages	4
ISBN (Electronic)	9782874870606
Publication status	Published - 10 Jan 2021
Event	15th European Microwave Integrated Circuits Conference (EuMIC 2020) - Utrecht, Netherlands Duration: 11 Jan 2021 → 15 Jan 2021 Conference number: 15

Conference

Conference	15th European Microwave Integrated Circuits Conference (EuMIC 2020)
Abbreviated title	EuMIC 2020
Country/Territory	Netherlands
City	Utrecht
Period	11/01/21 → 15/01/21

Keywords

65nm CMOS
CML frequency divider
phase-locked loop
voltage-controlled oscillator

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https://ieeexplore.ieee.org/document/9337426

Cite this

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title = "A PLL Frequency Synthesizer in 65 nm CMOS for 60 GHz Sliding-IF Transceiver",

abstract = "This paper presents an integer Phase-Locked Loop chip for 802.15.3c sliding-IF transceiver. The PLL is composed of a voltage-controlled oscillator, a current-mode logic divide-by-2, a programmable frequency divider, a phase/frequency detector, a charge pump, and an on-chip loop filter. The proposed PLL chip is fabricated using a 65 nm CMOS process, and the chip size is 1.27 mm2. The locking range of the proposed PLL is 23.328 25.92 GHz, the measured phase noise is-98.8 dBc/Hz@1 MHz, reference spur is-62.4 dBc. The power consumption of the PLL is 45.6 mW including the output buffer.",

keywords = "65nm CMOS, CML frequency divider, phase-locked loop, voltage-controlled oscillator",

author = "Yang Liu and Zhiqun Li and Hao Gao",

year = "2021",

month = jan,

day = "10",

language = "English",

pages = "221--224",

booktitle = "2020 15th European Microwave Integrated Circuits Conference (EuMIC)",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "15th European Microwave Integrated Circuits Conference (EuMIC 2020), EuMIC 2020 ; Conference date: 11-01-2021 Through 15-01-2021",

}

Liu, Y, Li, Z & Gao, H 2021, A PLL Frequency Synthesizer in 65 nm CMOS for 60 GHz Sliding-IF Transceiver. in 2020 15th European Microwave Integrated Circuits Conference (EuMIC)., 9337426, Institute of Electrical and Electronics Engineers, pp. 221-224, 15th European Microwave Integrated Circuits Conference (EuMIC 2020), Utrecht, Netherlands, 11/01/21. <https://ieeexplore.ieee.org/document/9337426>

A PLL Frequency Synthesizer in 65 nm CMOS for 60 GHz Sliding-IF Transceiver. / Liu, Yang; Li, Zhiqun; Gao, Hao.

2020 15th European Microwave Integrated Circuits Conference (EuMIC). Institute of Electrical and Electronics Engineers, 2021. p. 221-224 9337426.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A PLL Frequency Synthesizer in 65 nm CMOS for 60 GHz Sliding-IF Transceiver

AU - Liu, Yang

AU - Li, Zhiqun

AU - Gao, Hao

N1 - Conference code: 15

PY - 2021/1/10

Y1 - 2021/1/10

N2 - This paper presents an integer Phase-Locked Loop chip for 802.15.3c sliding-IF transceiver. The PLL is composed of a voltage-controlled oscillator, a current-mode logic divide-by-2, a programmable frequency divider, a phase/frequency detector, a charge pump, and an on-chip loop filter. The proposed PLL chip is fabricated using a 65 nm CMOS process, and the chip size is 1.27 mm2. The locking range of the proposed PLL is 23.328 25.92 GHz, the measured phase noise is-98.8 dBc/Hz@1 MHz, reference spur is-62.4 dBc. The power consumption of the PLL is 45.6 mW including the output buffer.

AB - This paper presents an integer Phase-Locked Loop chip for 802.15.3c sliding-IF transceiver. The PLL is composed of a voltage-controlled oscillator, a current-mode logic divide-by-2, a programmable frequency divider, a phase/frequency detector, a charge pump, and an on-chip loop filter. The proposed PLL chip is fabricated using a 65 nm CMOS process, and the chip size is 1.27 mm2. The locking range of the proposed PLL is 23.328 25.92 GHz, the measured phase noise is-98.8 dBc/Hz@1 MHz, reference spur is-62.4 dBc. The power consumption of the PLL is 45.6 mW including the output buffer.

KW - 65nm CMOS

KW - CML frequency divider

KW - phase-locked loop

KW - voltage-controlled oscillator

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M3 - Conference contribution

AN - SCOPUS:85100915864

SP - 221

EP - 224

BT - 2020 15th European Microwave Integrated Circuits Conference (EuMIC)

PB - Institute of Electrical and Electronics Engineers

T2 - 15th European Microwave Integrated Circuits Conference (EuMIC 2020)

Y2 - 11 January 2021 through 15 January 2021

ER -

A PLL Frequency Synthesizer in 65 nm CMOS for 60 GHz Sliding-IF Transceiver

Abstract

Conference

Keywords

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