Abstract
This paper presents an integer Phase-Locked Loop chip for 802.15.3c sliding-IF transceiver. The PLL is composed of a voltage-controlled oscillator, a current-mode logic divide-by-2, a programmable frequency divider, a phase/frequency detector, a charge pump, and an on-chip loop filter. The proposed PLL chip is fabricated using a 65 nm CMOS process, and the chip size is 1.27 mm2. The locking range of the proposed PLL is 23.328 25.92 GHz, the measured phase noise is-98.8 dBc/Hz@1 MHz, reference spur is-62.4 dBc. The power consumption of the PLL is 45.6 mW including the output buffer.
Original language | English |
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Title of host publication | 2020 15th European Microwave Integrated Circuits Conference (EuMIC) |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 221-224 |
Number of pages | 4 |
ISBN (Electronic) | 9782874870606 |
Publication status | Published - 10 Jan 2021 |
Event | 15th European Microwave Integrated Circuits Conference (EuMIC 2020) - Utrecht, Netherlands Duration: 11 Jan 2021 → 15 Jan 2021 Conference number: 15 |
Conference
Conference | 15th European Microwave Integrated Circuits Conference (EuMIC 2020) |
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Abbreviated title | EuMIC 2020 |
Country/Territory | Netherlands |
City | Utrecht |
Period | 11/01/21 → 15/01/21 |
Keywords
- 65nm CMOS
- CML frequency divider
- phase-locked loop
- voltage-controlled oscillator