@inproceedings{bab580f6e002495888446db491e960c8,
title = "A pattern based methodology for the design and implementation of multiplexed Master-Slave devices at the system-level; Use-case: Modeling a Level-2 Cache IP module at transaction level",
keywords = "cache storage, formal specification, LRU replacement algorithm, Motorola MPC2605 L2Cache, SystemC, commercial-off-the-shelf based development, hierarchical state machines, level-2 cache IP module, multiplexed master-slave device, pattern based methodology, set-associative cache mapping, software simulation models, technical specification document, virtual prototype, Algorithm design and analysis, Arrays, IP networks, Multiplexing, Object oriented modeling, Program processors, Random access memory, Design Patterns, ESL, L2Cache, TLM",
author = "S. Menon and J. Suryaprasad",
year = "2010",
month = nov,
day = "1",
doi = "10.1109/NESEA.2010.5678054",
language = "English",
pages = "1--6",
booktitle = "2010 IEEE International Conference on Networked Embedded Systems for Enterprise Applications",
}