A pattern based methodology for the design and implementation of multiplexed Master-Slave devices at the system-level; Use-case: Modeling a Level-2 Cache IP module at transaction level

S. Menon, J. Suryaprasad

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Original languageEnglish
Title of host publication2010 IEEE International Conference on Networked Embedded Systems for Enterprise Applications
Pages1-6
Number of pages6
DOIs
Publication statusPublished - 1 Nov 2010
Externally publishedYes

Keywords

  • cache storage
  • formal specification
  • LRU replacement algorithm
  • Motorola MPC2605 L2Cache
  • SystemC
  • commercial-off-the-shelf based development
  • hierarchical state machines
  • level-2 cache IP module
  • multiplexed master-slave device
  • pattern based methodology
  • set-associative cache mapping
  • software simulation models
  • technical specification document
  • virtual prototype
  • Algorithm design and analysis
  • Arrays
  • IP networks
  • Multiplexing
  • Object oriented modeling
  • Program processors
  • Random access memory
  • Design Patterns
  • ESL
  • L2Cache
  • TLM

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