Abstract
This paper proposes a passive switched-capacitor single-ended-to-differential-converter (SDC) as a front-end of a differential SAR ADC to enable digitization of single-ended signals. Compared to active SDC solutions or single-ended SAR ADCs, the proposed solution offers the smallest total capacitance as well as best power efficiency and least chip area. A noise analysis further shows that the passive SDC does not result in a noise penalty of the overall system. A prototype implementation in 65nm CMOS achieves a figure-of-merit of 6.1fJ/conversion-step at 20MS/s, while reaching an SNDR of 54.7dB up to Nyquist and occupying a chip area of only 60μm × 36μm.
Original language | English |
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Title of host publication | 2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021 - Proceedings |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 288-291 |
Number of pages | 4 |
ISBN (Electronic) | 9781665424615 |
DOIs | |
Publication status | Published - 13 Sept 2021 |
Event | 2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021 - Virtual, East Lansing, United States Duration: 9 Aug 2021 → 11 Aug 2021 |
Conference
Conference | 2021 IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2021 |
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Country/Territory | United States |
City | Virtual, East Lansing |
Period | 9/08/21 → 11/08/21 |
Bibliographical note
Funding Information:This work is part of the POSITION-II project funded by the ECSEL Joint Undertaking under grant number Ecsel-783132-Position-II-2017-IA.
Funding
This work is part of the POSITION-II project funded by the ECSEL Joint Undertaking under grant number Ecsel-783132-Position-II-2017-IA.