A parallel architecture for ray-racing with an embedded intersection algorithm

A. Solon Nery, N. Nedjah, M.G.F. Felipe, L. Jozwiak

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

3 Citations (Scopus)

Abstract

Real time rendering of three-dimensional scenes in Ray Tracing is a hard problem. However, parallel implementations have been enabling real time performance, as the algorithm can be highly parallelized. Thus, a custom parallel design in hardware is likely to achieve a good performance. In this paper, we further improve the GridRT architecture overall performance by embedding the ray-triangle intersection computation into the precessing elements that form the architecture. Low cost and high rendering performance are the main concerns in this novel design. The results show that the execution time of each intersection computation is reduced by at least 50%, while the area cost is practically unchanged or even reduced when compared to the original GridRT implementation.
Original languageEnglish
Title of host publicationProceedings of the 2011 International Symposium on Circuits and Systems (ISCAS 2011), 15-18 May 2011, Rio de Janeiro, Brazil
Place of PublicationLos Alamitos, USA
PublisherIEEE Computer Society
Pages1491-1494
DOIs
Publication statusPublished - 2011
Event2011 IEEE International Symposium on Circuits and Systems (ISCAS 2011) - Rio de Janeiro, Brazil
Duration: 15 May 201118 May 2011

Conference

Conference2011 IEEE International Symposium on Circuits and Systems (ISCAS 2011)
Abbreviated titleISCAS 2011
CountryBrazil
CityRio de Janeiro
Period15/05/1118/05/11

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