A novel timing-error based approach for high speed highly linear Mixing-DAC architectures

E. Bechthum, G.I. Radulov, J. Briaire, G. Geelen, A.H.M. Roermund, van

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

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Abstract

In current steering Mixing-DACs with local mixing, timing errors between the current cells is a major concern. This paper considers two types of random timing errors: delay and duty-cycle. Analysis shows that the Mixing-DAC is sensitive to delay errors, but much less sensitive to duty-cycle errors. For the required high spectral purity of future 4GHz multicarrier GSM (SFDRRBW =85dBc), the delay spread s(delay) should be
Original languageEnglish
Title of host publicationProceedings of the 2014 IEEE International Symposium on Circuits and Systems (ISCAS 2014), 1-5 June 2014, Melbourne, Australia
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages942-945
ISBN (Print)978-1-4799-3431-7
DOIs
Publication statusPublished - 2014

Cite this

Bechthum, E., Radulov, G. I., Briaire, J., Geelen, G., & Roermund, van, A. H. M. (2014). A novel timing-error based approach for high speed highly linear Mixing-DAC architectures. In Proceedings of the 2014 IEEE International Symposium on Circuits and Systems (ISCAS 2014), 1-5 June 2014, Melbourne, Australia (pp. 942-945). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISCAS.2014.6865292