A novel timing-error based approach for high speed highly linear Mixing-DAC architectures

E. Bechthum, G.I. Radulov, J. Briaire, G. Geelen, A.H.M. Roermund, van

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

4 Citations (Scopus)
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In current steering Mixing-DACs with local mixing, timing errors between the current cells is a major concern. This paper considers two types of random timing errors: delay and duty-cycle. Analysis shows that the Mixing-DAC is sensitive to delay errors, but much less sensitive to duty-cycle errors. For the required high spectral purity of future 4GHz multicarrier GSM (SFDRRBW =85dBc), the delay spread s(delay) should be
Original languageEnglish
Title of host publicationProceedings of the 2014 IEEE International Symposium on Circuits and Systems (ISCAS 2014), 1-5 June 2014, Melbourne, Australia
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Print)978-1-4799-3431-7
Publication statusPublished - 2014

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