A novel test time reduction algorithm for test architecture design for core-based system chips

Sandeep K. Goel, E.J. Marinissen

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

7 Citations (Scopus)

Abstract

This paper deals with the design of SoC test architectures which are efficient with respect to required ATE vector memory depth and test application time. We advocate the usage of a TestRail architecture, as this architecture, unlike others, allows not only for efficient core-internal testing, but also for efficient testing of the circuitry external to the cores. We present a novel heuristic algorithm that effectively optimizes the TestRail architecture for a given SoC by efficiently determining the number of TestRails and their widths, the assignment of cores to the TestRails, and the wrapper design per core. Experimental results for four benchmark SoCs show that, compared to previously published algorithms, we obtain comparable or better test times at negligible compute time.
Original languageEnglish
Title of host publicationProceedings of the Seventh IEEE European Test Workshop
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages7-12
Number of pages6
ISBN (Print)0-7695-1715-3
DOIs
Publication statusPublished - 2002
Externally publishedYes
Event7th IEEE European Test Workshop - Corfu, Greece
Duration: 26 May 200229 May 2002

Conference

Conference7th IEEE European Test Workshop
Country/TerritoryGreece
CityCorfu
Period26/05/0229/05/02

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