A novel complementary push-push frequency doubler with negative resistor conversion gain enhancement

Y. Liu, Z. Li, H. Gao, Q. Li, Z. Wang

Research output: Contribution to journalArticleAcademicpeer-review

2 Citations (Scopus)
394 Downloads (Pure)

Abstract

This letter presents a 48 GHz frequency doubler in a 65 nm CMOS technology. The proposed frequency doubler is composed of a complementary push-push structure with negative resistance circuit for conversion gain enhancement. The maximum measured conversion gain reaches −6.1 dB at 48 GHz output frequency, and the 3-dB bandwidth is 40∼54 GHz. The fundamental rejection is above 29.5 dB. The size of the proposed frequency doubler chip is 0.72 × 0.36 mm2The total power consumption is 16 mW.

Original languageEnglish
Article number20170674
Number of pages10
JournalIEICE Electronics Express
Volume14
Issue number15
DOIs
Publication statusPublished - 2017

Fingerprint

Frequency doublers
resistors
Resistors
augmentation
negative resistance circuits
Negative resistance
Electric power utilization
rejection
Bandwidth
CMOS
Networks (circuits)
chips
bandwidth
output

Keywords

  • CMOS
  • Complementary push-push
  • Frequency doubler
  • Negative resistor

Cite this

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title = "A novel complementary push-push frequency doubler with negative resistor conversion gain enhancement",
abstract = "This letter presents a 48 GHz frequency doubler in a 65 nm CMOS technology. The proposed frequency doubler is composed of a complementary push-push structure with negative resistance circuit for conversion gain enhancement. The maximum measured conversion gain reaches −6.1 dB at 48 GHz output frequency, and the 3-dB bandwidth is 40∼54 GHz. The fundamental rejection is above 29.5 dB. The size of the proposed frequency doubler chip is 0.72 × 0.36 mm2The total power consumption is 16 mW.",
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language = "English",
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A novel complementary push-push frequency doubler with negative resistor conversion gain enhancement. / Liu, Y.; Li, Z.; Gao, H.; Li, Q.; Wang, Z.

In: IEICE Electronics Express, Vol. 14, No. 15, 20170674, 2017.

Research output: Contribution to journalArticleAcademicpeer-review

TY - JOUR

T1 - A novel complementary push-push frequency doubler with negative resistor conversion gain enhancement

AU - Liu, Y.

AU - Li, Z.

AU - Gao, H.

AU - Li, Q.

AU - Wang, Z.

PY - 2017

Y1 - 2017

N2 - This letter presents a 48 GHz frequency doubler in a 65 nm CMOS technology. The proposed frequency doubler is composed of a complementary push-push structure with negative resistance circuit for conversion gain enhancement. The maximum measured conversion gain reaches −6.1 dB at 48 GHz output frequency, and the 3-dB bandwidth is 40∼54 GHz. The fundamental rejection is above 29.5 dB. The size of the proposed frequency doubler chip is 0.72 × 0.36 mm2The total power consumption is 16 mW.

AB - This letter presents a 48 GHz frequency doubler in a 65 nm CMOS technology. The proposed frequency doubler is composed of a complementary push-push structure with negative resistance circuit for conversion gain enhancement. The maximum measured conversion gain reaches −6.1 dB at 48 GHz output frequency, and the 3-dB bandwidth is 40∼54 GHz. The fundamental rejection is above 29.5 dB. The size of the proposed frequency doubler chip is 0.72 × 0.36 mm2The total power consumption is 16 mW.

KW - CMOS

KW - Complementary push-push

KW - Frequency doubler

KW - Negative resistor

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DO - 10.1587/elex.14.20170674

M3 - Article

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