A non-intrusive online FPGA test scheme using a hardwired network on chip

M.A. Wahlah, K.G.W. Goossens

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review


Modern Field Programmable Gate Arrays (FPGAs) posses small features, and have gained popularity in mission-critical systems. However, due to small FPGA features and harsh external conditions that can be faced by a mission-critical system, an FPGA chip can suffer from faults. This in turn raises the need to test an FPGA to ensure a reliable system performance. However, a mission-critical system requires that the test process should be non-intrusive, i.e., applications & FPGA regions that are not being tested remain unaffected. Hence, an online test scheme is required that not only verifies the correctness of an FPGA, but also does not degrade the performance of other, running FPGA applications. In this paper, we propose a Hardwired Network on Chip (HWNoC) as the Test Access Mechanism (TAM). Our online test scheme uses a HWNoC, to perform real-time streaming of test data that is non-intrusive to other communication traffic. Additionally, our online test scheme exhibits approx. 18 and 29 times lower spatial and temporal overheads as compared to existing schemes, respectively.
Original languageEnglish
Title of host publicationProceedings of the 14th Euromicro Conference on Digital System Design (DSD 2011), 31 August - 2 September 2011, Oulu, Finland
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
ISBN (Print)978-1-4577-1048-3
Publication statusPublished - 2011
Event14th Euromicro Conference on Digital System Design (DSD 2011) - Oulu, Finland
Duration: 31 Aug 20112 Sept 2011
Conference number: 14


Conference14th Euromicro Conference on Digital System Design (DSD 2011)
Abbreviated titleDSD 2011
Other"Architectures, Methods and Tools"
Internet address


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