Abstract
This paper presents a new technique to lower the computational cost of the electrothermal (ET) analysis of a large on-chip power distribution network. It is based on a node reduction strategy following a preliminary efficient steady-state solution of the ET problem. After a proper classification of nodes according to temperature and voltage drop ranges, a reduced network is then produced by means of clustering and topological network transformations, and is available for any static/dynamic analysis. Due to the achievable reduction ratios, it possible to lower by order of magnitudes the computational cost at very good accuracies. A case-study is provided where a power grid of 4 millions of nodes is reduced by a factor of 180 (electrical network) and 500 (thermal network).
Original language | English |
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Title of host publication | SPI 2015 - 19th IEEE Workshop on Signal and Power Integrity |
Publisher | Institute of Electrical and Electronics Engineers |
Number of pages | 4 |
ISBN (Electronic) | 9781467365819 |
DOIs | |
Publication status | Published - 2 Sept 2015 |
Externally published | Yes |
Event | 19th IEEE Workshop on Signal and Power Integrity, SPI 2015 - Berlin, Germany Duration: 10 May 2015 → 13 May 2015 |
Conference
Conference | 19th IEEE Workshop on Signal and Power Integrity, SPI 2015 |
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Country/Territory | Germany |
City | Berlin |
Period | 10/05/15 → 13/05/15 |
Bibliographical note
Publisher Copyright:© 2015 IEEE.
Keywords
- Electrothermal analysis
- IR-drop
- model order reduction
- On-chip power distribution networks