A new architecture for low-power high-speed pipelined ADCs using double-sampling and opamp-sharing techniques

S. Abdinia; M. Yavari

doi:10.1109/ICECS.2009.5410909

A new architecture for low-power high-speed pipelined ADCs using double-sampling and opamp-sharing techniques

S. Abdinia, M. Yavari

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

3 Citations (Scopus)

Abstract

This paper presents a low-voltage low-power pipelined ADC with 1V supply voltage in a 90nm CMOS process. A new architecture is proposed to reduce the power consumption in high-speed pipelined analog-to-digital converters (ADCs). The presented architecture utilizes a combination of two current power-reduction techniques, double sampling and amplifier sharing. To decrease the power dissipation more efficiently, the stage scaling technique has been applied to the ADC and dynamic comparators have been used in sub-ADCs. Using this approach, a 10-bit 200MSample/s pipelined ADC has been designed in a 90nm CMOS technology. HSPICE simulation results show a signal-to-noise plus distortion ratio (SNDR) of 58.5dB with a 9.375MHz, 1-VP-P,diff input signal while consuming only 30.9mW power from a 1V supply voltage.

Original language	English
Title of host publication	Proceedings of the 16th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2009), 13-16 December 2009, Yasmine Hammamet, Tunesia
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	395-398
ISBN (Print)	978-1-4244-5090-9
DOIs	https://doi.org/10.1109/ICECS.2009.5410909
Publication status	Published - 2009

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10.1109/ICECS.2009.5410909

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Abdinia, S., & Yavari, M. (2009). A new architecture for low-power high-speed pipelined ADCs using double-sampling and opamp-sharing techniques. In Proceedings of the 16th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2009), 13-16 December 2009, Yasmine Hammamet, Tunesia (pp. 395-398). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ICECS.2009.5410909

Abdinia, S. ; Yavari, M. / A new architecture for low-power high-speed pipelined ADCs using double-sampling and opamp-sharing techniques. Proceedings of the 16th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2009), 13-16 December 2009, Yasmine Hammamet, Tunesia. Piscataway : Institute of Electrical and Electronics Engineers, 2009. pp. 395-398

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abstract = "This paper presents a low-voltage low-power pipelined ADC with 1V supply voltage in a 90nm CMOS process. A new architecture is proposed to reduce the power consumption in high-speed pipelined analog-to-digital converters (ADCs). The presented architecture utilizes a combination of two current power-reduction techniques, double sampling and amplifier sharing. To decrease the power dissipation more efficiently, the stage scaling technique has been applied to the ADC and dynamic comparators have been used in sub-ADCs. Using this approach, a 10-bit 200MSample/s pipelined ADC has been designed in a 90nm CMOS technology. HSPICE simulation results show a signal-to-noise plus distortion ratio (SNDR) of 58.5dB with a 9.375MHz, 1-VP-P,diff input signal while consuming only 30.9mW power from a 1V supply voltage.",

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Abdinia, S & Yavari, M 2009, A new architecture for low-power high-speed pipelined ADCs using double-sampling and opamp-sharing techniques. in Proceedings of the 16th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2009), 13-16 December 2009, Yasmine Hammamet, Tunesia. Institute of Electrical and Electronics Engineers, Piscataway, pp. 395-398. https://doi.org/10.1109/ICECS.2009.5410909

A new architecture for low-power high-speed pipelined ADCs using double-sampling and opamp-sharing techniques. / Abdinia, S.; Yavari, M.
Proceedings of the 16th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2009), 13-16 December 2009, Yasmine Hammamet, Tunesia. Piscataway: Institute of Electrical and Electronics Engineers, 2009. p. 395-398.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AB - This paper presents a low-voltage low-power pipelined ADC with 1V supply voltage in a 90nm CMOS process. A new architecture is proposed to reduce the power consumption in high-speed pipelined analog-to-digital converters (ADCs). The presented architecture utilizes a combination of two current power-reduction techniques, double sampling and amplifier sharing. To decrease the power dissipation more efficiently, the stage scaling technique has been applied to the ADC and dynamic comparators have been used in sub-ADCs. Using this approach, a 10-bit 200MSample/s pipelined ADC has been designed in a 90nm CMOS technology. HSPICE simulation results show a signal-to-noise plus distortion ratio (SNDR) of 58.5dB with a 9.375MHz, 1-VP-P,diff input signal while consuming only 30.9mW power from a 1V supply voltage.

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Abdinia S, Yavari M. A new architecture for low-power high-speed pipelined ADCs using double-sampling and opamp-sharing techniques. In Proceedings of the 16th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2009), 13-16 December 2009, Yasmine Hammamet, Tunesia. Piscataway: Institute of Electrical and Electronics Engineers. 2009. p. 395-398 doi: 10.1109/ICECS.2009.5410909

A new architecture for low-power high-speed pipelined ADCs using double-sampling and opamp-sharing techniques

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