Abstract
A phase-locked loop (PLL) frequency synthesizer architecture for multiple-band applications is presented. A dynamically-controlled switched tuning voltage-controlled oscillator (VCO) is used to achieve superior frequency range and phase noise performance over a conventional PLL. Implemented in 1.4 µm CMOS, the PLL has a 111-290 MHz range, phase noise of -92.3 dBc/Hz at a 50 kHz offset, and dissipates 9 mW from a 2.7 V supply
Original language | English |
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Title of host publication | Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems, 2000, 8-11 August 200, Lansing, Michigan |
Place of Publication | New York |
Publisher | Institute of Electrical and Electronics Engineers |
Pages | 818-821 |
Volume | 2 |
ISBN (Print) | 0-7803-6475-9 |
DOIs | |
Publication status | Published - 2000 |
Externally published | Yes |