A monitoring-aware network-on-chip design flow

C. Ciordas, M.A Hansson, K.G.W. Goossens, A.A. Basten

Research output: Contribution to journalArticleAcademicpeer-review

16 Citations (Scopus)


Networks-on-chip (NoC) are a scalable interconnect solution for systems on chip and are rapidly becoming reality. Monitoring is a key enabler for debugging or performance analysis and quality-of-service techniques. The NoC design problem and the NoC monitoring problem cannot be treated in isolation. We propose a monitoring-aware NoC design flow able to take into account the monitoring requirements in general. We illustrate our flow with a debug driven monitoring case study of transaction monitoring. By treating the NoC design and monitoring problems in synergy, the area cost of monitoring can be limited to 3–20% in general. We also investigate run-time configuration options for the NoC monitoring system resulting in acceptable configuration times.
Original languageEnglish
Pages (from-to)397-410
Number of pages14
JournalJournal of Systems Architecture
Issue number3-4
Publication statusPublished - 2008


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