A Modified Asymmetric Switched-Capacitor Multilevel Inverter Topology with voltage boosting Capability

Mu  Anas; Anzar  Ahmad; Adil  Sarwar; Anuradha Tomar

doi:10.1109/UPCON47278.2019.8980012

A Modified Asymmetric Switched-Capacitor Multilevel Inverter Topology with voltage boosting Capability

Mu Anas , Anzar Ahmad, Adil Sarwar (Supervisor), Anuradha Tomar (Supervisor)

Electrical Energy Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

In this paper, a modified asymmetric switched-capacitor based MLI topology employing Switched-Capacitor DC/DC converter (SCC) as a level generator is proposed. The topology has the ability of self-voltage boosting and self-balancing of capacitors voltage. Moreover, it does not require an auxiliary circuit or capacitor voltage balancing algorithm. The comparison of this topology with other existing reduced device topologies in terms of numbers of gate driver circuits, power electronic switches, diodes, and capacitors has been done. To verify the feasibility and performance of this topology, the simulation is performed in MATLAB ^®/Simulink 2017b platform.

Original language	English
Title of host publication	2019 International Conference on Electrical, Electronics and Computer Engineering (UPCON)
Publisher	IEEE Press
ISBN (Electronic)	978-1-7281-3455-0
DOIs	https://doi.org/10.1109/UPCON47278.2019.8980012
Publication status	Published - Nov 2019
Event	2019 International Conference on Electrical, Electronics and Computer Engineering (UPCON) - Aligarh, India Duration: 8 Nov 2019 → 10 Nov 2019

Conference

Conference	2019 International Conference on Electrical, Electronics and Computer Engineering (UPCON)
Abbreviated title	UPCON 2019
Country	India
City	Aligarh
Period	8/11/19 → 10/11/19

Keywords

multilevel inverter
selective harmonic elimination
self-boosting
switched capacitor
total harmonic distortion

Access to Document

10.1109/UPCON47278.2019.8980012

Link to publication in Scopus

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Cite this

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title = "A Modified Asymmetric Switched-Capacitor Multilevel Inverter Topology with voltage boosting Capability",

abstract = "In this paper, a modified asymmetric switched-capacitor based MLI topology employing Switched-Capacitor DC/DC converter (SCC) as a level generator is proposed. The topology has the ability of self-voltage boosting and self-balancing of capacitors voltage. Moreover, it does not require an auxiliary circuit or capacitor voltage balancing algorithm. The comparison of this topology with other existing reduced device topologies in terms of numbers of gate driver circuits, power electronic switches, diodes, and capacitors has been done. To verify the feasibility and performance of this topology, the simulation is performed in MATLAB {\textregistered}/Simulink 2017b platform. ",

keywords = "multilevel inverter, selective harmonic elimination, self-boosting, switched capacitor, total harmonic distortion",

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Anas , M, Ahmad, A, Sarwar, A & Tomar, A 2019, A Modified Asymmetric Switched-Capacitor Multilevel Inverter Topology with voltage boosting Capability. in 2019 International Conference on Electrical, Electronics and Computer Engineering (UPCON)., 8980012, IEEE Press, 2019 International Conference on Electrical, Electronics and Computer Engineering (UPCON), Aligarh, India, 8/11/19. https://doi.org/10.1109/UPCON47278.2019.8980012

A Modified Asymmetric Switched-Capacitor Multilevel Inverter Topology with voltage boosting Capability. / Anas , Mu ; Ahmad, Anzar ; Sarwar, Adil (Supervisor); Tomar, Anuradha (Supervisor).

2019 International Conference on Electrical, Electronics and Computer Engineering (UPCON). IEEE Press, 2019. 8980012.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AB - In this paper, a modified asymmetric switched-capacitor based MLI topology employing Switched-Capacitor DC/DC converter (SCC) as a level generator is proposed. The topology has the ability of self-voltage boosting and self-balancing of capacitors voltage. Moreover, it does not require an auxiliary circuit or capacitor voltage balancing algorithm. The comparison of this topology with other existing reduced device topologies in terms of numbers of gate driver circuits, power electronic switches, diodes, and capacitors has been done. To verify the feasibility and performance of this topology, the simulation is performed in MATLAB ®/Simulink 2017b platform.

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