A method for testing a memory array and a memory-based device so testable with a fault response signalizing mode for when finding predetermined correspondence between fault patterns signalizing one such fault pattern only in the form of a compressed response

E.J. Marinissen (Inventor), G.E.A. Lousberg (Inventor), P. Wielage (Inventor)

Research output: PatentPatent publication

Abstract

A memory array, and in particular, an embedded memory array is tested by interfacing to a stimulus generator and a response evaluator pair. In a non-test condition the pair is steered in a transparent mode, and in a test condition in a stimulus generating mode and a response evaluating mode respectively. In a subsequent array repair condition row- and/or column-based repair intervention are allowed. In particular, the evaluator will evaluate correspondence between successive fault patterns, and further in a fault response signalizing mode to external circuitry on the basis of a predetermined correspondence between an earlier fault pattern and a later fault pattern signalize one of the two compared patterns only in the form of a lossless compressed response pattern.

Original languageEnglish
Patent numberWO0108161
IPCG11C 29/ 44 A I
Priority date22/07/99
Publication statusPublished - 1 Feb 2001
Externally publishedYes

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