A manufacturable sub-50nm PMOSFET technology

J. J.G.P. Loo, Y. V. Ponomarev, M. Kaiser, M. A. Verheijen, F. N. Cubaynes, C. J.J. Dachs

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

One of the major problems during the processing of PMOS devices is the excessive diffusion of boron source and drain regions. Plasma enhanced CVD can be used to reduce the thermal budget associated with layer depositions between source/drain implants and back end. It also gives a possibility to selectively etch deposited layers to allow novel processing sequences. Here we study these possibilities and show that by using highquality PECVD depositions, we can engineer the appropriate for sub-50nm generation PMOS device architectures.

Original languageEnglish
Title of host publicationEuropean Solid-State Device Research Conference
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages147-150
Number of pages4
ISBN (Print)2914601018
DOIs
Publication statusPublished - 1 Jan 2001
Externally publishedYes
Event31st European Solid-State Device Research Conference, ESSDERC 2001 - Nuremberg, Germany
Duration: 11 Sep 200113 Sep 2001

Conference

Conference31st European Solid-State Device Research Conference, ESSDERC 2001
CountryGermany
CityNuremberg
Period11/09/0113/09/01

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  • Cite this

    Loo, J. J. G. P., Ponomarev, Y. V., Kaiser, M., Verheijen, M. A., Cubaynes, F. N., & Dachs, C. J. J. (2001). A manufacturable sub-50nm PMOSFET technology. In European Solid-State Device Research Conference (pp. 147-150). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ESSDERC.2001.195222