A manufacturable sub-50nm PMOSFET technology

J. J.G.P. Loo; Y. V. Ponomarev; M. Kaiser; M. A. Verheijen; F. N. Cubaynes; C. J.J. Dachs

doi:10.1109/ESSDERC.2001.195222

A manufacturable sub-50nm PMOSFET technology

J. J.G.P. Loo, Y. V. Ponomarev, M. Kaiser, M. A. Verheijen, F. N. Cubaynes, C. J.J. Dachs

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

One of the major problems during the processing of PMOS devices is the excessive diffusion of boron source and drain regions. Plasma enhanced CVD can be used to reduce the thermal budget associated with layer depositions between source/drain implants and back end. It also gives a possibility to selectively etch deposited layers to allow novel processing sequences. Here we study these possibilities and show that by using highquality PECVD depositions, we can engineer the appropriate for sub-50nm generation PMOS device architectures.

Original language	English
Title of host publication	European Solid-State Device Research Conference
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	147-150
Number of pages	4
ISBN (Print)	2914601018
DOIs	https://doi.org/10.1109/ESSDERC.2001.195222
Publication status	Published - 1 Jan 2001
Externally published	Yes
Event	31st European Solid-State Device Research Conference, ESSDERC 2001 - Nuremberg, Germany Duration: 11 Sept 2001 → 13 Sept 2001

Conference

Conference	31st European Solid-State Device Research Conference, ESSDERC 2001
Country/Territory	Germany
City	Nuremberg
Period	11/09/01 → 13/09/01

Access to Document

10.1109/ESSDERC.2001.195222

Cite this

@inproceedings{eb889d49e9bd4374a0c5dd360c930f66,

title = "A manufacturable sub-50nm PMOSFET technology",

abstract = "One of the major problems during the processing of PMOS devices is the excessive diffusion of boron source and drain regions. Plasma enhanced CVD can be used to reduce the thermal budget associated with layer depositions between source/drain implants and back end. It also gives a possibility to selectively etch deposited layers to allow novel processing sequences. Here we study these possibilities and show that by using highquality PECVD depositions, we can engineer the appropriate for sub-50nm generation PMOS device architectures.",

author = "Loo, {J. J.G.P.} and Ponomarev, {Y. V.} and M. Kaiser and Verheijen, {M. A.} and Cubaynes, {F. N.} and Dachs, {C. J.J.}",

year = "2001",

month = jan,

day = "1",

doi = "10.1109/ESSDERC.2001.195222",

language = "English",

isbn = "2914601018",

pages = "147--150",

booktitle = "European Solid-State Device Research Conference",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "31st European Solid-State Device Research Conference, ESSDERC 2001 ; Conference date: 11-09-2001 Through 13-09-2001",

}

Loo, JJGP, Ponomarev, YV, Kaiser, M, Verheijen, MA, Cubaynes, FN & Dachs, CJJ 2001, A manufacturable sub-50nm PMOSFET technology. in European Solid-State Device Research Conference. Institute of Electrical and Electronics Engineers, Piscataway, pp. 147-150, 31st European Solid-State Device Research Conference, ESSDERC 2001, Nuremberg, Germany, 11/09/01. https://doi.org/10.1109/ESSDERC.2001.195222

TY - GEN

T1 - A manufacturable sub-50nm PMOSFET technology

AU - Loo, J. J.G.P.

AU - Ponomarev, Y. V.

AU - Kaiser, M.

AU - Verheijen, M. A.

AU - Cubaynes, F. N.

AU - Dachs, C. J.J.

PY - 2001/1/1

Y1 - 2001/1/1

N2 - One of the major problems during the processing of PMOS devices is the excessive diffusion of boron source and drain regions. Plasma enhanced CVD can be used to reduce the thermal budget associated with layer depositions between source/drain implants and back end. It also gives a possibility to selectively etch deposited layers to allow novel processing sequences. Here we study these possibilities and show that by using highquality PECVD depositions, we can engineer the appropriate for sub-50nm generation PMOS device architectures.

AB - One of the major problems during the processing of PMOS devices is the excessive diffusion of boron source and drain regions. Plasma enhanced CVD can be used to reduce the thermal budget associated with layer depositions between source/drain implants and back end. It also gives a possibility to selectively etch deposited layers to allow novel processing sequences. Here we study these possibilities and show that by using highquality PECVD depositions, we can engineer the appropriate for sub-50nm generation PMOS device architectures.

UR - http://www.scopus.com/inward/record.url?scp=84907486330&partnerID=8YFLogxK

U2 - 10.1109/ESSDERC.2001.195222

DO - 10.1109/ESSDERC.2001.195222

M3 - Conference contribution

AN - SCOPUS:84907486330

SN - 2914601018

SP - 147

EP - 150

BT - European Solid-State Device Research Conference

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 31st European Solid-State Device Research Conference, ESSDERC 2001

Y2 - 11 September 2001 through 13 September 2001

ER -

A manufacturable sub-50nm PMOSFET technology

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