A low-power highly-digitized receiver for 2.4-GHz-band GFSK applications

H.J. Bergveld; K.M.M. van Kaam; D.M.W. Leenaerts; K.J.P. Philips; A.W.P. Vaassen; G. Wetzker

doi:10.1109/RFIC.2004.1320617

A low-power highly-digitized receiver for 2.4-GHz-band GFSK applications

H.J. Bergveld, K.M.M. van Kaam, D.M.W. Leenaerts, K.J.P. Philips, A.W.P. Vaassen, G. Wetzker

Research output: Contribution to conference › Paper › Academic

9 Citations (Scopus)

Abstract

This paper describes the design and measurement results of a low-power highly-digitized receiver for GSFK-modulated input signals at 2.4 GHz. The RF front-end is based on a low-IF architecture and does not require any variable-gain or filtering blocks. The full dynamic range of the low-IF signal is converted into the digital domain by a low-power high-resolution time-continuous ΣΔ ADC. This leads to a linear receive chain without limiters. The digital block performs channel filtering and demodulation. The high degree of digitization leads to design flexibility with respect to changing standards and scalability in future CMOS generations. The receiver has been realized in a standard 0.18-μm CMOS process and measures 3.5 mm². The only external components are an antenna filter and a crystal. The power consumption is only 32 mW, which is at least a factor of two lower than state-of-the-art CMOS receivers.

Original language	English
Pages	347-350
Number of pages	4
DOIs	https://doi.org/10.1109/RFIC.2004.1320617
Publication status	Published - 2004
Externally published	Yes
Event	2004 IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2004) - Forth Worth, United States Duration: 6 Jun 2004 → 8 Jun 2004

Conference

Conference	2004 IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2004)
Abbreviated title	RFIC 2004
Country/Territory	United States
City	Forth Worth
Period	6/06/04 → 8/06/04

Keywords

CMOS integrated circuits
Demodulation
UHF receivers
Wireless LAN

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10.1109/RFIC.2004.1320617

Cite this

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title = "A low-power highly-digitized receiver for 2.4-GHz-band GFSK applications",

abstract = "This paper describes the design and measurement results of a low-power highly-digitized receiver for GSFK-modulated input signals at 2.4 GHz. The RF front-end is based on a low-IF architecture and does not require any variable-gain or filtering blocks. The full dynamic range of the low-IF signal is converted into the digital domain by a low-power high-resolution time-continuous ΣΔ ADC. This leads to a linear receive chain without limiters. The digital block performs channel filtering and demodulation. The high degree of digitization leads to design flexibility with respect to changing standards and scalability in future CMOS generations. The receiver has been realized in a standard 0.18-μm CMOS process and measures 3.5 mm2. The only external components are an antenna filter and a crystal. The power consumption is only 32 mW, which is at least a factor of two lower than state-of-the-art CMOS receivers.",

keywords = "CMOS integrated circuits, Demodulation, UHF receivers, Wireless LAN",

author = "H.J. Bergveld and {van Kaam}, K.M.M. and D.M.W. Leenaerts and K.J.P. Philips and A.W.P. Vaassen and G. Wetzker",

year = "2004",

doi = "10.1109/RFIC.2004.1320617",

language = "English",

pages = "347--350",

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AU - Bergveld, H.J.

AU - van Kaam, K.M.M.

AU - Leenaerts, D.M.W.

AU - Philips, K.J.P.

AU - Vaassen, A.W.P.

AU - Wetzker, G.

PY - 2004

Y1 - 2004

N2 - This paper describes the design and measurement results of a low-power highly-digitized receiver for GSFK-modulated input signals at 2.4 GHz. The RF front-end is based on a low-IF architecture and does not require any variable-gain or filtering blocks. The full dynamic range of the low-IF signal is converted into the digital domain by a low-power high-resolution time-continuous ΣΔ ADC. This leads to a linear receive chain without limiters. The digital block performs channel filtering and demodulation. The high degree of digitization leads to design flexibility with respect to changing standards and scalability in future CMOS generations. The receiver has been realized in a standard 0.18-μm CMOS process and measures 3.5 mm2. The only external components are an antenna filter and a crystal. The power consumption is only 32 mW, which is at least a factor of two lower than state-of-the-art CMOS receivers.

AB - This paper describes the design and measurement results of a low-power highly-digitized receiver for GSFK-modulated input signals at 2.4 GHz. The RF front-end is based on a low-IF architecture and does not require any variable-gain or filtering blocks. The full dynamic range of the low-IF signal is converted into the digital domain by a low-power high-resolution time-continuous ΣΔ ADC. This leads to a linear receive chain without limiters. The digital block performs channel filtering and demodulation. The high degree of digitization leads to design flexibility with respect to changing standards and scalability in future CMOS generations. The receiver has been realized in a standard 0.18-μm CMOS process and measures 3.5 mm2. The only external components are an antenna filter and a crystal. The power consumption is only 32 mW, which is at least a factor of two lower than state-of-the-art CMOS receivers.

KW - CMOS integrated circuits

KW - Demodulation

KW - UHF receivers

KW - Wireless LAN

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T2 - 2004 IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2004)

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A low-power highly-digitized receiver for 2.4-GHz-band GFSK applications

Abstract

Conference

Keywords

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