A low-power frontend system for fetal ECG monitoring applications

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Abstract

This paper presents a three-channel frontend system for fetal monitoring applications which includes three amplification chains, an ADC and all power management circuitry needed to feed the different building blocks from a single 1.4V supply. The specifications of the proposed system (0.38μVrms equivalent input noise, 74.5dB dynamic range and 0.5 to 200Hz signal bandwidth) are determined according to the properties of the fetal electrocardiogram (fECG) signal and realistic user scenarios. A low-power noise-reconfigurable preamplifier topology exploiting power optimization in both voltage and current domain is used, to achieve a Power Efficiency Factor (PEF) of 2.2 for the whole amplification chain. The 12bit SAR ADC is optimized for high resolution and power efficiency. The frontend system is designed in a 0.18μm CMOS process. Simulation results show that that each of the three amplification channels provides a total gain of 60dB a bandwidth of 200Hz, with an input equivalent noise of 0.38μVrms. The ADC provides 11.7bit ENOB and a FoM of 14fJ/step, while its sample speed can vary from 500Hz to 10kHz. The whole system consumes a power of 7.8μW when configured for the fECG application.

Original languageEnglish
Title of host publicationProceedings - 2015 6th IEEE International Workshop on Advances in Sensors and Interfaces, IWASI 2015, 18-19 June 2015, Gallipoli, Italy
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages87-91
Number of pages5
ISBN (Print)9781479989805
DOIs
Publication statusPublished - 10 Aug 2015
Event6th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI 2015) - Grand Hotel Costa Brada, Gallipoli, Italy
Duration: 18 Jun 201519 Jun 2015
Conference number: 6
http://iwasi2015.poliba.it/

Workshop

Workshop6th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI 2015)
Abbreviated titleIWASI 2015
CountryItaly
CityGallipoli
Period18/06/1519/06/15
Internet address

Fingerprint

Electrocardiography
Amplification
Monitoring
Fetal monitoring
Bandwidth
Topology
Specifications
Electric potential

Cite this

Song, S., Rooijakkers, M. J., Harpe, P., Rabotti, C., Mischi, M., Van Roermund, A. H. M., & Cantatore, E. (2015). A low-power frontend system for fetal ECG monitoring applications. In Proceedings - 2015 6th IEEE International Workshop on Advances in Sensors and Interfaces, IWASI 2015, 18-19 June 2015, Gallipoli, Italy (pp. 87-91). [7184931] Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/IWASI.2015.7184931
Song, S. ; Rooijakkers, M. J. ; Harpe, P. ; Rabotti, C. ; Mischi, M. ; Van Roermund, A. H M ; Cantatore, E. / A low-power frontend system for fetal ECG monitoring applications. Proceedings - 2015 6th IEEE International Workshop on Advances in Sensors and Interfaces, IWASI 2015, 18-19 June 2015, Gallipoli, Italy. Piscataway : Institute of Electrical and Electronics Engineers, 2015. pp. 87-91
@inproceedings{870031d006284aca925cf480a348301b,
title = "A low-power frontend system for fetal ECG monitoring applications",
abstract = "This paper presents a three-channel frontend system for fetal monitoring applications which includes three amplification chains, an ADC and all power management circuitry needed to feed the different building blocks from a single 1.4V supply. The specifications of the proposed system (0.38μVrms equivalent input noise, 74.5dB dynamic range and 0.5 to 200Hz signal bandwidth) are determined according to the properties of the fetal electrocardiogram (fECG) signal and realistic user scenarios. A low-power noise-reconfigurable preamplifier topology exploiting power optimization in both voltage and current domain is used, to achieve a Power Efficiency Factor (PEF) of 2.2 for the whole amplification chain. The 12bit SAR ADC is optimized for high resolution and power efficiency. The frontend system is designed in a 0.18μm CMOS process. Simulation results show that that each of the three amplification channels provides a total gain of 60dB a bandwidth of 200Hz, with an input equivalent noise of 0.38μVrms. The ADC provides 11.7bit ENOB and a FoM of 14fJ/step, while its sample speed can vary from 500Hz to 10kHz. The whole system consumes a power of 7.8μW when configured for the fECG application.",
author = "S. Song and Rooijakkers, {M. J.} and P. Harpe and C. Rabotti and M. Mischi and {Van Roermund}, {A. H M} and E. Cantatore",
year = "2015",
month = "8",
day = "10",
doi = "10.1109/IWASI.2015.7184931",
language = "English",
isbn = "9781479989805",
pages = "87--91",
booktitle = "Proceedings - 2015 6th IEEE International Workshop on Advances in Sensors and Interfaces, IWASI 2015, 18-19 June 2015, Gallipoli, Italy",
publisher = "Institute of Electrical and Electronics Engineers",
address = "United States",

}

Song, S, Rooijakkers, MJ, Harpe, P, Rabotti, C, Mischi, M, Van Roermund, AHM & Cantatore, E 2015, A low-power frontend system for fetal ECG monitoring applications. in Proceedings - 2015 6th IEEE International Workshop on Advances in Sensors and Interfaces, IWASI 2015, 18-19 June 2015, Gallipoli, Italy., 7184931, Institute of Electrical and Electronics Engineers, Piscataway, pp. 87-91, 6th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI 2015), Gallipoli, Italy, 18/06/15. https://doi.org/10.1109/IWASI.2015.7184931

A low-power frontend system for fetal ECG monitoring applications. / Song, S.; Rooijakkers, M. J.; Harpe, P.; Rabotti, C.; Mischi, M.; Van Roermund, A. H M; Cantatore, E.

Proceedings - 2015 6th IEEE International Workshop on Advances in Sensors and Interfaces, IWASI 2015, 18-19 June 2015, Gallipoli, Italy. Piscataway : Institute of Electrical and Electronics Engineers, 2015. p. 87-91 7184931.

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

TY - GEN

T1 - A low-power frontend system for fetal ECG monitoring applications

AU - Song, S.

AU - Rooijakkers, M. J.

AU - Harpe, P.

AU - Rabotti, C.

AU - Mischi, M.

AU - Van Roermund, A. H M

AU - Cantatore, E.

PY - 2015/8/10

Y1 - 2015/8/10

N2 - This paper presents a three-channel frontend system for fetal monitoring applications which includes three amplification chains, an ADC and all power management circuitry needed to feed the different building blocks from a single 1.4V supply. The specifications of the proposed system (0.38μVrms equivalent input noise, 74.5dB dynamic range and 0.5 to 200Hz signal bandwidth) are determined according to the properties of the fetal electrocardiogram (fECG) signal and realistic user scenarios. A low-power noise-reconfigurable preamplifier topology exploiting power optimization in both voltage and current domain is used, to achieve a Power Efficiency Factor (PEF) of 2.2 for the whole amplification chain. The 12bit SAR ADC is optimized for high resolution and power efficiency. The frontend system is designed in a 0.18μm CMOS process. Simulation results show that that each of the three amplification channels provides a total gain of 60dB a bandwidth of 200Hz, with an input equivalent noise of 0.38μVrms. The ADC provides 11.7bit ENOB and a FoM of 14fJ/step, while its sample speed can vary from 500Hz to 10kHz. The whole system consumes a power of 7.8μW when configured for the fECG application.

AB - This paper presents a three-channel frontend system for fetal monitoring applications which includes three amplification chains, an ADC and all power management circuitry needed to feed the different building blocks from a single 1.4V supply. The specifications of the proposed system (0.38μVrms equivalent input noise, 74.5dB dynamic range and 0.5 to 200Hz signal bandwidth) are determined according to the properties of the fetal electrocardiogram (fECG) signal and realistic user scenarios. A low-power noise-reconfigurable preamplifier topology exploiting power optimization in both voltage and current domain is used, to achieve a Power Efficiency Factor (PEF) of 2.2 for the whole amplification chain. The 12bit SAR ADC is optimized for high resolution and power efficiency. The frontend system is designed in a 0.18μm CMOS process. Simulation results show that that each of the three amplification channels provides a total gain of 60dB a bandwidth of 200Hz, with an input equivalent noise of 0.38μVrms. The ADC provides 11.7bit ENOB and a FoM of 14fJ/step, while its sample speed can vary from 500Hz to 10kHz. The whole system consumes a power of 7.8μW when configured for the fECG application.

UR - http://www.scopus.com/inward/record.url?scp=84944219257&partnerID=8YFLogxK

U2 - 10.1109/IWASI.2015.7184931

DO - 10.1109/IWASI.2015.7184931

M3 - Conference contribution

AN - SCOPUS:84944219257

SN - 9781479989805

SP - 87

EP - 91

BT - Proceedings - 2015 6th IEEE International Workshop on Advances in Sensors and Interfaces, IWASI 2015, 18-19 June 2015, Gallipoli, Italy

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

ER -

Song S, Rooijakkers MJ, Harpe P, Rabotti C, Mischi M, Van Roermund AHM et al. A low-power frontend system for fetal ECG monitoring applications. In Proceedings - 2015 6th IEEE International Workshop on Advances in Sensors and Interfaces, IWASI 2015, 18-19 June 2015, Gallipoli, Italy. Piscataway: Institute of Electrical and Electronics Engineers. 2015. p. 87-91. 7184931 https://doi.org/10.1109/IWASI.2015.7184931