A low power 0.25 μm CMOS technology

P. H. Woerlee; C. A.H. Juffermans; H. Lifka; W. Manders; H. Pomp; G. Paulzen; A. J. Walker; R. Woltjer

doi:10.1109/IEDM.1992.307302

A low power 0.25 μm CMOS technology

P. H. Woerlee, C. A.H. Juffermans, H. Lifka, W. Manders, H. Pomp, G. Paulzen, A. J. Walker, R. Woltjer

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

8 Citations (Scopus)

Abstract

A 0.25 μ m CMOS technology with scaled LOCOS isolation, twin implanted well, 7.5 nm gate oxide thickness, surface channel NMOS and PMOS devices, shallow n- and p-junctions and thin TiSi₂ salicide is described. The technology is optimized for a reduced supply voltage of 2.5 V. The device design and fabrication, device characterisation and inverter delay are presented.

Original language	English
Title of host publication	1992 International Technical Digest on Electron Devices Meeting, IEDM 1992
Publisher	Institute of Electrical and Electronics Engineers
Pages	31-34
Number of pages	4
ISBN (Print)	0780308174
DOIs	https://doi.org/10.1109/IEDM.1992.307302
Publication status	Published - 1 Jan 1992
Externally published	Yes
Event	1992 IEEE International Electron Devices Meeting, IEDM 1992 - San Francisco, United States Duration: 13 Dec 1992 → 16 Dec 1992

Conference

Conference	1992 IEEE International Electron Devices Meeting, IEDM 1992
Country/Territory	United States
City	San Francisco
Period	13/12/92 → 16/12/92
Other	International Technical Digest on Electron Devices Meeting

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10.1109/IEDM.1992.307302

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title = "A low power 0.25 μm CMOS technology",

abstract = "A 0.25 μ m CMOS technology with scaled LOCOS isolation, twin implanted well, 7.5 nm gate oxide thickness, surface channel NMOS and PMOS devices, shallow n- and p-junctions and thin TiSi2 salicide is described. The technology is optimized for a reduced supply voltage of 2.5 V. The device design and fabrication, device characterisation and inverter delay are presented.",

author = "Woerlee, {P. H.} and Juffermans, {C. A.H.} and H. Lifka and W. Manders and H. Pomp and G. Paulzen and Walker, {A. J.} and R. Woltjer",

year = "1992",

month = jan,

day = "1",

doi = "10.1109/IEDM.1992.307302",

language = "English",

isbn = "0780308174",

pages = "31--34",

booktitle = "1992 International Technical Digest on Electron Devices Meeting, IEDM 1992",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "1992 IEEE International Electron Devices Meeting, IEDM 1992 ; Conference date: 13-12-1992 Through 16-12-1992",

}

Woerlee, PH, Juffermans, CAH, Lifka, H, Manders, W, Pomp, H, Paulzen, G, Walker, AJ & Woltjer, R 1992, A low power 0.25 μm CMOS technology. in 1992 International Technical Digest on Electron Devices Meeting, IEDM 1992., 307302, Institute of Electrical and Electronics Engineers, pp. 31-34, 1992 IEEE International Electron Devices Meeting, IEDM 1992, San Francisco, California, United States, 13/12/92. https://doi.org/10.1109/IEDM.1992.307302

TY - GEN

T1 - A low power 0.25 μm CMOS technology

AU - Woerlee, P. H.

AU - Juffermans, C. A.H.

AU - Lifka, H.

AU - Manders, W.

AU - Pomp, H.

AU - Paulzen, G.

AU - Walker, A. J.

AU - Woltjer, R.

PY - 1992/1/1

Y1 - 1992/1/1

N2 - A 0.25 μ m CMOS technology with scaled LOCOS isolation, twin implanted well, 7.5 nm gate oxide thickness, surface channel NMOS and PMOS devices, shallow n- and p-junctions and thin TiSi2 salicide is described. The technology is optimized for a reduced supply voltage of 2.5 V. The device design and fabrication, device characterisation and inverter delay are presented.

AB - A 0.25 μ m CMOS technology with scaled LOCOS isolation, twin implanted well, 7.5 nm gate oxide thickness, surface channel NMOS and PMOS devices, shallow n- and p-junctions and thin TiSi2 salicide is described. The technology is optimized for a reduced supply voltage of 2.5 V. The device design and fabrication, device characterisation and inverter delay are presented.

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U2 - 10.1109/IEDM.1992.307302

DO - 10.1109/IEDM.1992.307302

M3 - Conference contribution

AN - SCOPUS:84975335011

SN - 0780308174

SP - 31

EP - 34

BT - 1992 International Technical Digest on Electron Devices Meeting, IEDM 1992

PB - Institute of Electrical and Electronics Engineers

T2 - 1992 IEEE International Electron Devices Meeting, IEDM 1992

Y2 - 13 December 1992 through 16 December 1992

ER -

A low power 0.25 μm CMOS technology

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