This paper presents a broadband, static, 2:1 frequency divider in a bulk 90 nm CMOS LP (low-power) technology with maximum operating frequency of 35.5 GHz. The divider exhibits an enhanced input sensitivity, below 0 dBm, over a broad input range of 31 GHz and consumes 24 mA from a 1.2 V supply. The phase noise of the divider is -124.6 dBc/Hz at 1 MHz offset from the carrier.
|Title of host publication||IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2007 : 3 - 5 June 2007, Honolulu, Hawaii, USA|
|Place of Publication||Piscataway|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2007|