A hybrid design automation tool for SAR ADCs in IoT

Ming Ding, Pieter Harpe, Guibin Chen, Benjamin Busze, Yao-Hong Liu, Christian Bachmann, Kathleen Philips, Arthur van Roermund

Research output: Contribution to journalArticleAcademicpeer-review

Abstract

In this paper, a hybrid design automation tool for asynchronous successive approximation register analog-to-digital converters (SAR ADCs) in Internet-of-Things applications is presented. The circuit design-driven tool uses a top-down design approach and generates circuits from specification to layout automatically. A hybrid approach is introduced for different circuits of a SAR ADC: fully synthesized control logic; a script-based flow combining equations, library, and template-based design for the digital-to-analog converter; a lookup table approach combined with selective simulation-based fine tuning and template-based layout generation for the sample and hold; library-based comparator design and script-based layout generation. By balancing the automation and manual effort, the circuit design time is reduced from days down to minutes while still being able to maintain ADC performance. The proposed flow generated two ADC prototypes in 40-nm CMOS, an 8-bit 32 MS/s and a 12-bit 1 MS/s SAR ADC, and enabled excellent power efficiency. The two ADCs consume 187 and 16.7 μW at 1-V supply voltage, achieving 30.7 and 18.1 fJ/conversion-step, respectively.

LanguageEnglish
Pages2853-2862
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume26
Issue number12
DOIs
StatePublished - 1 Dec 2018

Fingerprint

Digital to analog conversion
Automation
Networks (circuits)
Table lookup
Internet of things
Tuning
Specifications
Electric potential

Keywords

  • Automation
  • Design automation
  • hybrid approach
  • Hybrid power systems
  • Layout
  • low power
  • Manuals
  • Mathematical model
  • successive approximation register analog-to-digital converter (SAR ADC).
  • Tools

Cite this

Ding, Ming ; Harpe, Pieter ; Chen, Guibin ; Busze, Benjamin ; Liu, Yao-Hong ; Bachmann, Christian ; Philips, Kathleen ; van Roermund, Arthur. / A hybrid design automation tool for SAR ADCs in IoT. In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2018 ; Vol. 26, No. 12. pp. 2853-2862
@article{462fa956639e40c0af5106b1c447a0c6,
title = "A hybrid design automation tool for SAR ADCs in IoT",
abstract = "In this paper, a hybrid design automation tool for asynchronous successive approximation register analog-to-digital converters (SAR ADCs) in Internet-of-Things applications is presented. The circuit design-driven tool uses a top-down design approach and generates circuits from specification to layout automatically. A hybrid approach is introduced for different circuits of a SAR ADC: fully synthesized control logic; a script-based flow combining equations, library, and template-based design for the digital-to-analog converter; a lookup table approach combined with selective simulation-based fine tuning and template-based layout generation for the sample and hold; library-based comparator design and script-based layout generation. By balancing the automation and manual effort, the circuit design time is reduced from days down to minutes while still being able to maintain ADC performance. The proposed flow generated two ADC prototypes in 40-nm CMOS, an 8-bit 32 MS/s and a 12-bit 1 MS/s SAR ADC, and enabled excellent power efficiency. The two ADCs consume 187 and 16.7 μW at 1-V supply voltage, achieving 30.7 and 18.1 fJ/conversion-step, respectively.",
keywords = "Automation, Design automation, hybrid approach, Hybrid power systems, Layout, low power, Manuals, Mathematical model, successive approximation register analog-to-digital converter (SAR ADC)., Tools",
author = "Ming Ding and Pieter Harpe and Guibin Chen and Benjamin Busze and Yao-Hong Liu and Christian Bachmann and Kathleen Philips and {van Roermund}, Arthur",
year = "2018",
month = "12",
day = "1",
doi = "10.1109/TVLSI.2018.2865404",
language = "English",
volume = "26",
pages = "2853--2862",
journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
issn = "1063-8210",
publisher = "Institute of Electrical and Electronics Engineers",
number = "12",

}

A hybrid design automation tool for SAR ADCs in IoT. / Ding, Ming; Harpe, Pieter; Chen, Guibin; Busze, Benjamin; Liu, Yao-Hong; Bachmann, Christian; Philips, Kathleen; van Roermund, Arthur.

In: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 26, No. 12, 01.12.2018, p. 2853-2862.

Research output: Contribution to journalArticleAcademicpeer-review

TY - JOUR

T1 - A hybrid design automation tool for SAR ADCs in IoT

AU - Ding,Ming

AU - Harpe,Pieter

AU - Chen,Guibin

AU - Busze,Benjamin

AU - Liu,Yao-Hong

AU - Bachmann,Christian

AU - Philips,Kathleen

AU - van Roermund,Arthur

PY - 2018/12/1

Y1 - 2018/12/1

N2 - In this paper, a hybrid design automation tool for asynchronous successive approximation register analog-to-digital converters (SAR ADCs) in Internet-of-Things applications is presented. The circuit design-driven tool uses a top-down design approach and generates circuits from specification to layout automatically. A hybrid approach is introduced for different circuits of a SAR ADC: fully synthesized control logic; a script-based flow combining equations, library, and template-based design for the digital-to-analog converter; a lookup table approach combined with selective simulation-based fine tuning and template-based layout generation for the sample and hold; library-based comparator design and script-based layout generation. By balancing the automation and manual effort, the circuit design time is reduced from days down to minutes while still being able to maintain ADC performance. The proposed flow generated two ADC prototypes in 40-nm CMOS, an 8-bit 32 MS/s and a 12-bit 1 MS/s SAR ADC, and enabled excellent power efficiency. The two ADCs consume 187 and 16.7 μW at 1-V supply voltage, achieving 30.7 and 18.1 fJ/conversion-step, respectively.

AB - In this paper, a hybrid design automation tool for asynchronous successive approximation register analog-to-digital converters (SAR ADCs) in Internet-of-Things applications is presented. The circuit design-driven tool uses a top-down design approach and generates circuits from specification to layout automatically. A hybrid approach is introduced for different circuits of a SAR ADC: fully synthesized control logic; a script-based flow combining equations, library, and template-based design for the digital-to-analog converter; a lookup table approach combined with selective simulation-based fine tuning and template-based layout generation for the sample and hold; library-based comparator design and script-based layout generation. By balancing the automation and manual effort, the circuit design time is reduced from days down to minutes while still being able to maintain ADC performance. The proposed flow generated two ADC prototypes in 40-nm CMOS, an 8-bit 32 MS/s and a 12-bit 1 MS/s SAR ADC, and enabled excellent power efficiency. The two ADCs consume 187 and 16.7 μW at 1-V supply voltage, achieving 30.7 and 18.1 fJ/conversion-step, respectively.

KW - Automation

KW - Design automation

KW - hybrid approach

KW - Hybrid power systems

KW - Layout

KW - low power

KW - Manuals

KW - Mathematical model

KW - successive approximation register analog-to-digital converter (SAR ADC).

KW - Tools

UR - http://www.scopus.com/inward/record.url?scp=85053302453&partnerID=8YFLogxK

U2 - 10.1109/TVLSI.2018.2865404

DO - 10.1109/TVLSI.2018.2865404

M3 - Article

VL - 26

SP - 2853

EP - 2862

JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

T2 - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems

SN - 1063-8210

IS - 12

ER -

Ding M, Harpe P, Chen G, Busze B, Liu Y-H, Bachmann C et al. A hybrid design automation tool for SAR ADCs in IoT. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2018 Dec 1;26(12):2853-2862. Available from, DOI: 10.1109/TVLSI.2018.2865404