A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling

Daniel Casini, Alessandro Biondi, Geoffrey Nelissen, Giorgio Buttazzo

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

When adopting multi-core systems for safety-critical applications, certification requirements mandate bounding the delays incurred in accessing shared resources. This is the case of global memories, whose access is often regulated by memory controllers optimized for average-case performance and not designed to be predictable. As a consequence, worst-case bounds on memory access delays often result to be too pessimistic, drastically reducing the advantage of having multiple cores. This paper proposes a fine-grained analysis of the memory contention experienced by parallel tasks running on a multi-core platform. To this end, an optimization problem is formulated to bound the memory interference by leveraging a three-phase execution model and holistically considering multiple memory transactions issued during each phase. Experimental results show the advantage in adopting the proposed approach on both synthetic task sets and benchmarks.

Original languageEnglish
Title of host publicationProceedings - 2020 IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020
PublisherInstitute of Electrical and Electronics Engineers
Pages239-252
Number of pages14
ISBN (Electronic)9781728154992
DOIs
Publication statusPublished - Apr 2020
Event26th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020 - Sydney, Australia
Duration: 21 Apr 202024 Apr 2020

Conference

Conference26th IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020
CountryAustralia
CitySydney
Period21/04/2024/04/20

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  • Cite this

    Casini, D., Biondi, A., Nelissen, G., & Buttazzo, G. (2020). A Holistic Memory Contention Analysis for Parallel Real-Time Tasks under Partitioned Scheduling. In Proceedings - 2020 IEEE Real-Time and Embedded Technology and Applications Symposium, RTAS 2020 (pp. 239-252). [9113115] Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/RTAS48715.2020.000-3