A high-performance SI memory cell

D.M.W. Leenaerts, A.J. Leeuwenburgh, G.G. Persoon

Research output: Contribution to journalArticleAcademicpeer-review

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Abstract

In this paper, we present a new type of switched current memory cell with a three phase clock cycle. The design technique is based on differential error matching, which leads to input currents between 50 and 85 PA. The conversion period is 700 ns, which is significantly lower, compared to other results presented in the literature, taking into account the error. Still higher speeds can be obtained by using shorter channel-length technologies. a high accuracy cell with measured errors less than 200 ppm for
Original languageEnglish
Pages (from-to)1404-1407
Number of pages4
JournalIEEE Journal of Solid-State Circuits
Volume29
Issue number11
DOIs
Publication statusPublished - 1994

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