A high performance and low energy intra prediction hardware for high efficiency video coding

Ercan Kalali; Yusuf Adibelli; Ilker Hamzaoglu

doi:10.1109/FPL.2012.6339161

A high performance and low energy intra prediction hardware for high efficiency video coding

Ercan Kalali
, Yusuf Adibelli
, Ilker Hamzaoglu

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

49 Citations (Scopus)

Abstract

Intra prediction algorithm in the recently developed High Efficiency Video Coding (HEVC) standard has very high computational complexity. Therefore, in this paper, we propose novel techniques for reducing amount of computations performed by HEVC intra prediction algorithm, and therefore reducing energy consumption of HEVC intra prediction hardware. The proposed techniques significantly reduce the amount of computations performed by 4x4 and 8x8 angular prediction modes with a small comparison overhead without any PSNR and bit rate loss. We also designed and implemented a high performance HEVC intra prediction hardware for 4x4 and 8x8 angular prediction modes including the proposed techniques using Verilog HDL, and mapped it to a Xilinx Virtex 6 FPGA. The proposed techniques significantly reduce the energy consumption of the proposed hardware on this FPGA.

Original language	English
Title of host publication	22nd International Conference on Field Programmable Logic and Applications (FPL)
Publisher	Institute of Electrical and Electronics Engineers
Pages	719-722
Number of pages	4
ISBN (Electronic)	978-1-4673-2256-0
ISBN (Print)	978-1-4673-2257-7
DOIs	https://doi.org/10.1109/FPL.2012.6339161
Publication status	Published - 25 Oct 2012
Externally published	Yes
Event	22nd International Conference on Field Programmable Logic and Applications, FPL 2012 - Oslo, Norway Duration: 29 Aug 2012 → 31 Aug 2012 Conference number: 22

Conference

Conference	22nd International Conference on Field Programmable Logic and Applications, FPL 2012
Abbreviated title	FPL 2012
Country/Territory	Norway
City	Oslo
Period	29/08/12 → 31/08/12

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

HEVC
Intra Prediction
Low Power Design

Access to Document

10.1109/FPL.2012.6339161

Cite this

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title = "A high performance and low energy intra prediction hardware for high efficiency video coding",

abstract = "Intra prediction algorithm in the recently developed High Efficiency Video Coding (HEVC) standard has very high computational complexity. Therefore, in this paper, we propose novel techniques for reducing amount of computations performed by HEVC intra prediction algorithm, and therefore reducing energy consumption of HEVC intra prediction hardware. The proposed techniques significantly reduce the amount of computations performed by 4x4 and 8x8 angular prediction modes with a small comparison overhead without any PSNR and bit rate loss. We also designed and implemented a high performance HEVC intra prediction hardware for 4x4 and 8x8 angular prediction modes including the proposed techniques using Verilog HDL, and mapped it to a Xilinx Virtex 6 FPGA. The proposed techniques significantly reduce the energy consumption of the proposed hardware on this FPGA.",

keywords = "HEVC, Intra Prediction, Low Power Design",

author = "Ercan Kalali and Yusuf Adibelli and Ilker Hamzaoglu",

year = "2012",

month = oct,

day = "25",

doi = "10.1109/FPL.2012.6339161",

language = "English",

isbn = "978-1-4673-2257-7",

pages = "719--722",

booktitle = "22nd International Conference on Field Programmable Logic and Applications (FPL)",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "22nd International Conference on Field Programmable Logic and Applications, FPL 2012, FPL 2012 ; Conference date: 29-08-2012 Through 31-08-2012",

}

Kalali, E, Adibelli, Y & Hamzaoglu, I 2012, A high performance and low energy intra prediction hardware for high efficiency video coding. in 22nd International Conference on Field Programmable Logic and Applications (FPL)., 6339161, Institute of Electrical and Electronics Engineers, pp. 719-722, 22nd International Conference on Field Programmable Logic and Applications, FPL 2012, Oslo, Norway, 29/08/12. https://doi.org/10.1109/FPL.2012.6339161

A high performance and low energy intra prediction hardware for high efficiency video coding. / Kalali, Ercan; Adibelli, Yusuf; Hamzaoglu, Ilker.
22nd International Conference on Field Programmable Logic and Applications (FPL). Institute of Electrical and Electronics Engineers, 2012. p. 719-722 6339161.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A high performance and low energy intra prediction hardware for high efficiency video coding

AU - Kalali, Ercan

AU - Adibelli, Yusuf

AU - Hamzaoglu, Ilker

N1 - Conference code: 22

PY - 2012/10/25

Y1 - 2012/10/25

N2 - Intra prediction algorithm in the recently developed High Efficiency Video Coding (HEVC) standard has very high computational complexity. Therefore, in this paper, we propose novel techniques for reducing amount of computations performed by HEVC intra prediction algorithm, and therefore reducing energy consumption of HEVC intra prediction hardware. The proposed techniques significantly reduce the amount of computations performed by 4x4 and 8x8 angular prediction modes with a small comparison overhead without any PSNR and bit rate loss. We also designed and implemented a high performance HEVC intra prediction hardware for 4x4 and 8x8 angular prediction modes including the proposed techniques using Verilog HDL, and mapped it to a Xilinx Virtex 6 FPGA. The proposed techniques significantly reduce the energy consumption of the proposed hardware on this FPGA.

AB - Intra prediction algorithm in the recently developed High Efficiency Video Coding (HEVC) standard has very high computational complexity. Therefore, in this paper, we propose novel techniques for reducing amount of computations performed by HEVC intra prediction algorithm, and therefore reducing energy consumption of HEVC intra prediction hardware. The proposed techniques significantly reduce the amount of computations performed by 4x4 and 8x8 angular prediction modes with a small comparison overhead without any PSNR and bit rate loss. We also designed and implemented a high performance HEVC intra prediction hardware for 4x4 and 8x8 angular prediction modes including the proposed techniques using Verilog HDL, and mapped it to a Xilinx Virtex 6 FPGA. The proposed techniques significantly reduce the energy consumption of the proposed hardware on this FPGA.

KW - HEVC

KW - Intra Prediction

KW - Low Power Design

UR - https://www.scopus.com/pages/publications/84870669983

U2 - 10.1109/FPL.2012.6339161

DO - 10.1109/FPL.2012.6339161

M3 - Conference contribution

SN - 978-1-4673-2257-7

SP - 719

EP - 722

BT - 22nd International Conference on Field Programmable Logic and Applications (FPL)

PB - Institute of Electrical and Electronics Engineers

T2 - 22nd International Conference on Field Programmable Logic and Applications, FPL 2012

Y2 - 29 August 2012 through 31 August 2012

ER -

A high performance and low energy intra prediction hardware for high efficiency video coding

Abstract

Conference

UN SDGs

Keywords

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