A hierarchical design automation concept for analog circuits

Gonenc Berkol; Engin Afacan; Gunhan Dundar; E.V. Fernandez

doi:10.1109/ICECS.2016.7841150

A hierarchical design automation concept for analog circuits

Gonenc Berkol, Engin Afacan, Gunhan Dundar, E.V. Fernandez

Integrated Circuits

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

1 Citation (Scopus)

Abstract

This paper presents a new approach to hierarchically synthesize analog circuits. In general, behavioral models are preferred at intermediate levels to reduce total synthesis time. However, there are problems associated with the usage of behavioral models such as significantly sacrificing the accuracy and costly preparation time for model generation. Therefore, a model-free approach is proposed, in which behavioral models are eliminated at higher level. Top level specifications and sub-block performances are optimized simultaneously during the synthesis process, where performance requirements of sub-blocks are arranged automatically. A third order low pass Butterworth filter is used as an example to show the effectiveness of the proposed approach.

Original language	English
Title of host publication	2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	133-136
Number of pages	4
ISBN (Electronic)	978-1-5090-6113-6
ISBN (Print)	978-1-5090-6114-3
DOIs	https://doi.org/10.1109/ICECS.2016.7841150
Publication status	Published - 2 Feb 2017
Event	23rd IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016 - Monte Carlo, Monaco Duration: 11 Dec 2016 → 14 Dec 2016 Conference number: 23

Conference

Conference	23rd IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016
Abbreviated title	ICES 2016
Country/Territory	Monaco
City	Monte Carlo
Period	11/12/16 → 14/12/16

Access to Document

10.1109/ICECS.2016.7841150

Cite this

@inproceedings{a868300187f3440a9013c965dfcecbc6,

title = "A hierarchical design automation concept for analog circuits",

abstract = "This paper presents a new approach to hierarchically synthesize analog circuits. In general, behavioral models are preferred at intermediate levels to reduce total synthesis time. However, there are problems associated with the usage of behavioral models such as significantly sacrificing the accuracy and costly preparation time for model generation. Therefore, a model-free approach is proposed, in which behavioral models are eliminated at higher level. Top level specifications and sub-block performances are optimized simultaneously during the synthesis process, where performance requirements of sub-blocks are arranged automatically. A third order low pass Butterworth filter is used as an example to show the effectiveness of the proposed approach.",

author = "Gonenc Berkol and Engin Afacan and Gunhan Dundar and E.V. Fernandez",

year = "2017",

month = feb,

day = "2",

doi = "10.1109/ICECS.2016.7841150",

language = "English",

isbn = "978-1-5090-6114-3",

pages = "133--136",

booktitle = "2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "23rd IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, ICES 2016 ; Conference date: 11-12-2016 Through 14-12-2016",

}

Berkol, G, Afacan, E, Dundar, G & Fernandez, EV 2017, A hierarchical design automation concept for analog circuits. in 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016., 7841150, Institute of Electrical and Electronics Engineers, Piscataway, pp. 133-136, 23rd IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016, Monte Carlo, Monaco, 11/12/16. https://doi.org/10.1109/ICECS.2016.7841150

A hierarchical design automation concept for analog circuits. / Berkol, Gonenc; Afacan, Engin; Dundar, Gunhan et al.

2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016. Piscataway : Institute of Electrical and Electronics Engineers, 2017. p. 133-136 7841150.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A hierarchical design automation concept for analog circuits

AU - Berkol, Gonenc

AU - Afacan, Engin

AU - Dundar, Gunhan

AU - Fernandez, E.V.

N1 - Conference code: 23

PY - 2017/2/2

Y1 - 2017/2/2

N2 - This paper presents a new approach to hierarchically synthesize analog circuits. In general, behavioral models are preferred at intermediate levels to reduce total synthesis time. However, there are problems associated with the usage of behavioral models such as significantly sacrificing the accuracy and costly preparation time for model generation. Therefore, a model-free approach is proposed, in which behavioral models are eliminated at higher level. Top level specifications and sub-block performances are optimized simultaneously during the synthesis process, where performance requirements of sub-blocks are arranged automatically. A third order low pass Butterworth filter is used as an example to show the effectiveness of the proposed approach.

AB - This paper presents a new approach to hierarchically synthesize analog circuits. In general, behavioral models are preferred at intermediate levels to reduce total synthesis time. However, there are problems associated with the usage of behavioral models such as significantly sacrificing the accuracy and costly preparation time for model generation. Therefore, a model-free approach is proposed, in which behavioral models are eliminated at higher level. Top level specifications and sub-block performances are optimized simultaneously during the synthesis process, where performance requirements of sub-blocks are arranged automatically. A third order low pass Butterworth filter is used as an example to show the effectiveness of the proposed approach.

UR - http://www.scopus.com/inward/record.url?scp=85015266024&partnerID=8YFLogxK

U2 - 10.1109/ICECS.2016.7841150

DO - 10.1109/ICECS.2016.7841150

M3 - Conference contribution

AN - SCOPUS:85015266024

SN - 978-1-5090-6114-3

SP - 133

EP - 136

BT - 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 23rd IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016

Y2 - 11 December 2016 through 14 December 2016

ER -

A hierarchical design automation concept for analog circuits

Abstract

Conference

Access to Document

Other files and links

Fingerprint

Cite this