A hierarchical design automation concept for analog circuits

Gonenc Berkol, Engin Afacan, Gunhan Dundar, E.V. Fernandez

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

Abstract

This paper presents a new approach to hierarchically synthesize analog circuits. In general, behavioral models are preferred at intermediate levels to reduce total synthesis time. However, there are problems associated with the usage of behavioral models such as significantly sacrificing the accuracy and costly preparation time for model generation. Therefore, a model-free approach is proposed, in which behavioral models are eliminated at higher level. Top level specifications and sub-block performances are optimized simultaneously during the synthesis process, where performance requirements of sub-blocks are arranged automatically. A third order low pass Butterworth filter is used as an example to show the effectiveness of the proposed approach.

Original languageEnglish
Title of host publication2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages133-136
Number of pages4
ISBN (Electronic)978-1-5090-6113-6
ISBN (Print)978-1-5090-6114-3
DOIs
Publication statusPublished - 2 Feb 2017
Event23rd IEEE International Conference on Electronics, Circuits and Systems (ICECS 2016) - Monte Carlo, Monaco
Duration: 11 Dec 201614 Dec 2016
Conference number: 23

Conference

Conference23rd IEEE International Conference on Electronics, Circuits and Systems (ICECS 2016)
Abbreviated titleICES 2016
CountryMonaco
CityMonte Carlo
Period11/12/1614/12/16

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    Berkol, G., Afacan, E., Dundar, G., & Fernandez, E. V. (2017). A hierarchical design automation concept for analog circuits. In 2016 IEEE International Conference on Electronics, Circuits and Systems, ICECS 2016 (pp. 133-136). [7841150] Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ICECS.2016.7841150