A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systems

M. Dev Gomony, J. Garside, B. Akesson, N. Audsley, K.G.W. Goossens

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

12 Citations (Scopus)

Abstract

Predictable arbitration policies, such as Time Division Multiplexing (TDM) and Round-Robin (RR), are used to provide firm real-time guarantees to clients sharing a single memory resource (DRAM) between the multiple memory clients in multi-core real-time systems. Traditional centralized implementations of predictable arbitration policies in a shared memory bus or interconnect are not scalable in terms of the number of clients. On the other hand, existing distributed memory interconnects are either globally arbitrated, which do not offer diverse service according to the heterogeneous client requirements, or locally arbitrated, which suffers from larger area, power and latency overhead. Moreover, selecting the right arbitration policy according to the diverse and dynamic client requirements in reusable platforms requires a generic re-configurable architecture supporting different arbitration policies. The main contributions in this paper are: (1) We propose a novel generic, scalable and globally arbitrated memory tree (GSMT) architecture for distributed implementation of several predictable arbitration policies. (2) We present an RTL-level implementation of Accounting and Priority assignment (APA) logic of GSMT that can be configured with five different arbitration policies typically used for shared memory access in real-time systems. (3) We compare the performance of GSMT with different centralized implementations by synthesizing the designs in a 40 nm process. Our experiments show that with 64 clients GSMT can run up to four times faster than traditional architectures and have over 51% and 37% reduction in area and power consumption, respectively.

Original languageEnglish
Title of host publicationProceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition, DATE 2015
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages193-198
Number of pages6
ISBN (Electronic)978-3-9815-3705-5
DOIs
Publication statusPublished - 22 Apr 2015
Event18th Design, Automation and Test in Europe Conference and Exhibition (DATE 2015) - Alpexpo Congress Centre, Grenoble, France
Duration: 9 Mar 201513 Mar 2015
Conference number: 18
https://www.date-conference.com/date15/

Conference

Conference18th Design, Automation and Test in Europe Conference and Exhibition (DATE 2015)
Abbreviated titleDATE 2015
Country/TerritoryFrance
CityGrenoble
Period9/03/1513/03/15
Internet address

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