A generic network on chip model

J. Schmaltz, D. Borrione

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    4 Citations (Scopus)


    We present a generic network on chip model (named GeNoC) intended to serve as a reference for the design and the validation of high level specifications of communication virtual modules. The definition of the model relies on three independent groups of constrained functions: routing and topology, scheduling, interfaces. The model identifies the sufficient constraints that these functions must satisfy in order to prove the correctness of GeNoC. Hence, one can concentrate his efforts on the design and the verification of one group. As long as the constraints are satisfied the overall system correctness is still valid. We show some concrete instances of GeNoC. One of them is a state-of-the-art network taken from industry.
    Original languageEnglish
    Title of host publicationTheorem Proving in Higher Order Logics
    Subtitle of host publication18th International Conference, TPHOLs 2005, Oxford, UK, August 22-25, 2005. Proceedings
    EditorsJ. Hurd, T.F. Melham
    Place of PublicationBerlin
    Number of pages16
    ISBN (Electronic)978-3-540-31820-0
    ISBN (Print)978-3-540-28372-0
    Publication statusPublished - 2006

    Publication series

    NameLecture Notes in Computer Science (LNCS)
    ISSN (Print)0302-9743
    ISSN (Electronic)1611-3349


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