A generic methodology to compute design sensitivity to SEU in SRAM-Based FPGA

Mahsa Mousavi; Hamid Reza Pourshaghaghi; Mohammad Tahghighi; Roel Jordans; Henk Corporaal

doi:10.1109/DSD.2018.00050

A generic methodology to compute design sensitivity to SEU in SRAM-Based FPGA

Mahsa Mousavi, Hamid Reza Pourshaghaghi, Mohammad Tahghighi, Roel Jordans, Henk Corporaal

Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

14 Citations (Scopus)

675 Downloads (Pure)

Abstract

Recently, SRAM-based FPGAs are widely used in aeronautic and space systems. As the adverse effects of radiations in space are much higher than in the Earth, developing fault tolerant techniques play crucial roles for the use of electronics in space. However, fault tolerance techniques might introduce additional penalties in area, power, performance and design time. In order to compromise between the overhead introduced by these techniques and system fault tolerance, a generic methodology for calculating design sensitivity to Single-Event Upset (SEU) is proposed in this paper. Separate schema and test-bench for evaluating effects of SEU in various types of FPGA memory are proposed in which both the raw device error rate and the vulnerability characteristic of the specific application mapped on the device are taken into account. Experimental results show that using our model in order to selectively add Triple Modular Redundancy (TMR) improve the design robustness only 18% less than full TMR while roughly introduces 69% less redundancy compared to full TMR for Fast Fourier Transform (FFT).

Original language	English
Title of host publication	Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018
Editors	Nikos Konofaos, Martin Novotny, Amund Skavhaug
Publisher	Institute of Electrical and Electronics Engineers
Pages	221-228
Number of pages	8
ISBN (Electronic)	9781538673768
DOIs	https://doi.org/10.1109/DSD.2018.00050
Publication status	Published - 12 Oct 2018
Event	21st Euromicro Conference on Digital System Design, DSD 2018 - Prague, Czech Republic Duration: 29 Aug 2018 → 31 Aug 2018 Conference number: 21 http://dsd-seaa2018.fit.cvut.cz/dsd/

Conference

Conference	21st Euromicro Conference on Digital System Design, DSD 2018
Abbreviated title	DSD 2018
Country/Territory	Czech Republic
City	Prague
Period	29/08/18 → 31/08/18
Internet address	http://dsd-seaa2018.fit.cvut.cz/dsd/

Keywords

Design vulnerability
Fault tolerance
FPGA
Raw device error rate
Simulation based injection
Single-Event Upset (SEU)

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10.1109/DSD.2018.00050

author versionFinal author version , 770 KBLicence: Unspecified

Cite this

Mousavi, M., Pourshaghaghi, H. R., Tahghighi, M., Jordans, R., & Corporaal, H. (2018). A generic methodology to compute design sensitivity to SEU in SRAM-Based FPGA. In N. Konofaos, M. Novotny, & A. Skavhaug (Eds.), Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018 (pp. 221-228). Article 8491821 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/DSD.2018.00050

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abstract = "Recently, SRAM-based FPGAs are widely used in aeronautic and space systems. As the adverse effects of radiations in space are much higher than in the Earth, developing fault tolerant techniques play crucial roles for the use of electronics in space. However, fault tolerance techniques might introduce additional penalties in area, power, performance and design time. In order to compromise between the overhead introduced by these techniques and system fault tolerance, a generic methodology for calculating design sensitivity to Single-Event Upset (SEU) is proposed in this paper. Separate schema and test-bench for evaluating effects of SEU in various types of FPGA memory are proposed in which both the raw device error rate and the vulnerability characteristic of the specific application mapped on the device are taken into account. Experimental results show that using our model in order to selectively add Triple Modular Redundancy (TMR) improve the design robustness only 18% less than full TMR while roughly introduces 69% less redundancy compared to full TMR for Fast Fourier Transform (FFT).",

keywords = "Design vulnerability, Fault tolerance, FPGA, Raw device error rate, Simulation based injection, Single-Event Upset (SEU)",

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Mousavi, M , Pourshaghaghi, HR, Tahghighi, M, Jordans, R & Corporaal, H 2018, A generic methodology to compute design sensitivity to SEU in SRAM-Based FPGA. in N Konofaos, M Novotny & A Skavhaug (eds), Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018., 8491821, Institute of Electrical and Electronics Engineers, pp. 221-228, 21st Euromicro Conference on Digital System Design, DSD 2018, Prague, Czech Republic, 29/08/18. https://doi.org/10.1109/DSD.2018.00050

A generic methodology to compute design sensitivity to SEU in SRAM-Based FPGA. / Mousavi, Mahsa ; Pourshaghaghi, Hamid Reza; Tahghighi, Mohammad et al.
Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018. ed. / Nikos Konofaos; Martin Novotny; Amund Skavhaug. Institute of Electrical and Electronics Engineers, 2018. p. 221-228 8491821.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Corporaal, Henk

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N2 - Recently, SRAM-based FPGAs are widely used in aeronautic and space systems. As the adverse effects of radiations in space are much higher than in the Earth, developing fault tolerant techniques play crucial roles for the use of electronics in space. However, fault tolerance techniques might introduce additional penalties in area, power, performance and design time. In order to compromise between the overhead introduced by these techniques and system fault tolerance, a generic methodology for calculating design sensitivity to Single-Event Upset (SEU) is proposed in this paper. Separate schema and test-bench for evaluating effects of SEU in various types of FPGA memory are proposed in which both the raw device error rate and the vulnerability characteristic of the specific application mapped on the device are taken into account. Experimental results show that using our model in order to selectively add Triple Modular Redundancy (TMR) improve the design robustness only 18% less than full TMR while roughly introduces 69% less redundancy compared to full TMR for Fast Fourier Transform (FFT).

AB - Recently, SRAM-based FPGAs are widely used in aeronautic and space systems. As the adverse effects of radiations in space are much higher than in the Earth, developing fault tolerant techniques play crucial roles for the use of electronics in space. However, fault tolerance techniques might introduce additional penalties in area, power, performance and design time. In order to compromise between the overhead introduced by these techniques and system fault tolerance, a generic methodology for calculating design sensitivity to Single-Event Upset (SEU) is proposed in this paper. Separate schema and test-bench for evaluating effects of SEU in various types of FPGA memory are proposed in which both the raw device error rate and the vulnerability characteristic of the specific application mapped on the device are taken into account. Experimental results show that using our model in order to selectively add Triple Modular Redundancy (TMR) improve the design robustness only 18% less than full TMR while roughly introduces 69% less redundancy compared to full TMR for Fast Fourier Transform (FFT).

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BT - Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018

A2 - Konofaos, Nikos

A2 - Novotny, Martin

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PB - Institute of Electrical and Electronics Engineers

T2 - 21st Euromicro Conference on Digital System Design, DSD 2018

Y2 - 29 August 2018 through 31 August 2018

ER -

Mousavi M , Pourshaghaghi HR, Tahghighi M, Jordans R , Corporaal H. A generic methodology to compute design sensitivity to SEU in SRAM-Based FPGA. In Konofaos N, Novotny M, Skavhaug A, editors, Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018. Institute of Electrical and Electronics Engineers. 2018. p. 221-228. 8491821 Epub 2018 Aug 29. doi: 10.1109/DSD.2018.00050

A generic methodology to compute design sensitivity to SEU in SRAM-Based FPGA

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