A generic methodology to compute design sensitivity to SEU in SRAM-Based FPGA

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Recently, SRAM-based FPGAs are widely used in aeronautic and space systems. As the adverse effects of radiations in space are much higher than in the Earth, developing fault tolerant techniques play crucial roles for the use of electronics in space. However, fault tolerance techniques might introduce additional penalties in area, power, performance and design time. In order to compromise between the overhead introduced by these techniques and system fault tolerance, a generic methodology for calculating design sensitivity to Single-Event Upset (SEU) is proposed in this paper. Separate schema and test-bench for evaluating effects of SEU in various types of FPGA memory are proposed in which both the raw device error rate and the vulnerability characteristic of the specific application mapped on the device are taken into account. Experimental results show that using our model in order to selectively add Triple Modular Redundancy (TMR) improve the design robustness only 18% less than full TMR while roughly introduces 69% less redundancy compared to full TMR for Fast Fourier Transform (FFT).

Original languageEnglish
Title of host publicationProceedings - 21st Euromicro Conference on Digital System Design, DSD 2018
EditorsNikos Konofaos, Martin Novotny, Amund Skavhaug
PublisherInstitute of Electrical and Electronics Engineers
Number of pages8
ISBN (Electronic)9781538673768
Publication statusPublished - 12 Oct 2018
Event21st Euromicro Conference on Digital System Design (DSD 2018) - Prague, Czech Republic
Duration: 29 Aug 201831 Aug 2018
Conference number: 21


Conference21st Euromicro Conference on Digital System Design (DSD 2018)
Abbreviated titleDSD 2018
Country/TerritoryCzech Republic
Internet address


  • Design vulnerability
  • Fault tolerance
  • FPGA
  • Raw device error rate
  • Simulation based injection
  • Single-Event Upset (SEU)


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