A general analysis on the timing jitter in D/A converters

K. Doris, A.H.M. Roermund, van, D.M.W. Leenaerts

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

21 Citations (Scopus)

Abstract

A general analysis on stochastic timing errors (clock or timing jitter) is presented for Digital to Analog Converters (DACs). The obtained results describe the effects of (non)correlated errors for given signal properties, and reveal the nature of the tradeoff between oversampling ratio, resolution and noise shaping in the context of noise-shaped DACs and Continuous-Time (CT) Sigma Delta (EA) ADCs. The importance of timing jitter for wideband DAC performance is exemplified with theory and simulations.
Original languageEnglish
Title of host publicationIEEE International Symposium on Circuits and systems (ISCAS)
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages117-120
Volume1
ISBN (Print)0-7803-7448-7
DOIs
Publication statusPublished - 2002

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