A general analysis on stochastic timing errors (clock or timing jitter) is presented for Digital to Analog Converters (DACs). The obtained results describe the effects of (non)correlated errors for given signal properties, and reveal the nature of the tradeoff between oversampling ratio, resolution and noise shaping in the context of noise-shaped DACs and Continuous-Time (CT) Sigma Delta (EA) ADCs. The importance of timing jitter for wideband DAC performance is exemplified with theory and simulations.
|Title of host publication||IEEE International Symposium on Circuits and systems (ISCAS)|
|Place of Publication||Piscataway|
|Publisher||Institute of Electrical and Electronics Engineers|
|Publication status||Published - 2002|