A general analysis on the timing jitter in D/A converters

K. Doris; A.H.M. Roermund, van; D.M.W. Leenaerts

doi:10.1109/ISCAS.2002.1009791

A general analysis on the timing jitter in D/A converters

K. Doris, A.H.M. Roermund, van, D.M.W. Leenaerts

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Abstract

A general analysis on stochastic timing errors (clock or timing jitter) is presented for Digital to Analog Converters (DACs). The obtained results describe the effects of (non)correlated errors for given signal properties, and reveal the nature of the tradeoff between oversampling ratio, resolution and noise shaping in the context of noise-shaped DACs and Continuous-Time (CT) Sigma Delta (EA) ADCs. The importance of timing jitter for wideband DAC performance is exemplified with theory and simulations.

Original language	English
Title of host publication	IEEE International Symposium on Circuits and systems (ISCAS)
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	117-120
Volume	1
ISBN (Print)	0-7803-7448-7
DOIs	https://doi.org/10.1109/ISCAS.2002.1009791
Publication status	Published - 2002

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10.1109/ISCAS.2002.1009791

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title = "A general analysis on the timing jitter in D/A converters",

abstract = "A general analysis on stochastic timing errors (clock or timing jitter) is presented for Digital to Analog Converters (DACs). The obtained results describe the effects of (non)correlated errors for given signal properties, and reveal the nature of the tradeoff between oversampling ratio, resolution and noise shaping in the context of noise-shaped DACs and Continuous-Time (CT) Sigma Delta (EA) ADCs. The importance of timing jitter for wideband DAC performance is exemplified with theory and simulations.",

author = "K. Doris and {Roermund, van}, A.H.M. and D.M.W. Leenaerts",

year = "2002",

doi = "10.1109/ISCAS.2002.1009791",

language = "English",

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booktitle = "IEEE International Symposium on Circuits and systems (ISCAS)",

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A general analysis on the timing jitter in D/A converters. / Doris, K.; Roermund, van, A.H.M.; Leenaerts, D.M.W.
IEEE International Symposium on Circuits and systems (ISCAS). Vol. 1 Piscataway: Institute of Electrical and Electronics Engineers, 2002. p. 117-120.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A general analysis on the timing jitter in D/A converters

AU - Doris, K.

AU - Roermund, van, A.H.M.

AU - Leenaerts, D.M.W.

PY - 2002

Y1 - 2002

N2 - A general analysis on stochastic timing errors (clock or timing jitter) is presented for Digital to Analog Converters (DACs). The obtained results describe the effects of (non)correlated errors for given signal properties, and reveal the nature of the tradeoff between oversampling ratio, resolution and noise shaping in the context of noise-shaped DACs and Continuous-Time (CT) Sigma Delta (EA) ADCs. The importance of timing jitter for wideband DAC performance is exemplified with theory and simulations.

AB - A general analysis on stochastic timing errors (clock or timing jitter) is presented for Digital to Analog Converters (DACs). The obtained results describe the effects of (non)correlated errors for given signal properties, and reveal the nature of the tradeoff between oversampling ratio, resolution and noise shaping in the context of noise-shaped DACs and Continuous-Time (CT) Sigma Delta (EA) ADCs. The importance of timing jitter for wideband DAC performance is exemplified with theory and simulations.

U2 - 10.1109/ISCAS.2002.1009791

DO - 10.1109/ISCAS.2002.1009791

M3 - Conference contribution

SN - 0-7803-7448-7

VL - 1

SP - 117

EP - 120

BT - IEEE International Symposium on Circuits and systems (ISCAS)

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

ER -

A general analysis on the timing jitter in D/A converters

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