A four-quadrant S2I switched-current multiplier

G. Manganaro, J. Pineda de Gyvez

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    Abstract

    The analysis, design, and implementation of a two-step current-sampling switched-current (S2I) multiplier is presented. The S2I technique has been employed to compensate analog errors due to charge injection as well as those arising from the finite output impedance. A thorough circuit analysis investigating the offset sources of the S2I cell and of the multiplier's nonlinearities sets up the platform to effectively design the multiplier and to avoid the use of feedback, or cascode techniques, to deal with channel modulation effects. The multiplier has been implemented using a 2-µm n-well MOSIS CMOS technology. Experimental results are in agreement with the theoretical findings. The following are brief highlights of the measurement results: (1) 0.425 millions of multiplications per second; (2) 1.7% total harmonic distortion for a sinusoidal of 35-µA (50 Hz); (3) 206 kHz of bandwidth; (4) 50 dB of SNR; and (5) 0.3-mW zero input power consumption for a ±3-V power supply. A complete set of detailed experimental results is provided in the paper
    Original languageEnglish
    Pages (from-to)791-799
    Number of pages9
    JournalIEEE Transactions on Circuits and Systems. II, Analog and Digital Signal Processing
    Volume45
    Issue number7
    DOIs
    Publication statusPublished - 1998

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