A forward body bias generator for digital CMOS circuits with supply voltage scaling

M. Meijer; J. Pineda de Gyvez; B. Kup; B. Uden, van; P. Bastiaansen; M. Lammers; M. Vertregt

doi:10.1109/ISCAS.2010.5537129

A forward body bias generator for digital CMOS circuits with supply voltage scaling

M. Meijer, J. Pineda de Gyvez, B. Kup, B. Uden, van, P. Bastiaansen, M. Lammers, M. Vertregt

Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

23 Citations (Scopus)

280 Downloads (Pure)

Abstract

We propose a new fully-integrated forward body bias (FBB) generator that holds its voltage constant relative to the (scalable) power supply of a digital IP. The generator is modular and can drive distinct digital IP block sizes in multiples of up to 1mm2. The design has been implemented in 90nm low-power CMOS. Our basic unit for driving digital IP blocks up to 1mm2 occupies a silicon area of 0.03mm2 only. The generator completes a 500mV FBB voltage step within 4µs. The bandwidth of the design is 570kHz. The active current of the FBB generator alone is about 177µA for a nominal process, 1.2V supply and 85°C. The standby current is as low as 72nA at 27°C.

Original language	English
Title of host publication	Proceedings of the 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 30 - June 2, 2010, Paris, France
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	2482-2485
ISBN (Print)	978-1-4244-5308-5
DOIs	https://doi.org/10.1109/ISCAS.2010.5537129
Publication status	Published - 2010

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Meijer, M., Pineda de Gyvez, J., Kup, B., Uden, van, B., Bastiaansen, P., Lammers, M., & Vertregt, M. (2010). A forward body bias generator for digital CMOS circuits with supply voltage scaling. In Proceedings of the 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 30 - June 2, 2010, Paris, France (pp. 2482-2485). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISCAS.2010.5537129

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title = "A forward body bias generator for digital CMOS circuits with supply voltage scaling",

abstract = "We propose a new fully-integrated forward body bias (FBB) generator that holds its voltage constant relative to the (scalable) power supply of a digital IP. The generator is modular and can drive distinct digital IP block sizes in multiples of up to 1mm2. The design has been implemented in 90nm low-power CMOS. Our basic unit for driving digital IP blocks up to 1mm2 occupies a silicon area of 0.03mm2 only. The generator completes a 500mV FBB voltage step within 4µs. The bandwidth of the design is 570kHz. The active current of the FBB generator alone is about 177µA for a nominal process, 1.2V supply and 85°C. The standby current is as low as 72nA at 27°C.",

author = "M. Meijer and {Pineda de Gyvez}, J. and B. Kup and {Uden, van}, B. and P. Bastiaansen and M. Lammers and M. Vertregt",

year = "2010",

doi = "10.1109/ISCAS.2010.5537129",

language = "English",

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pages = "2482--2485",

booktitle = "Proceedings of the 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 30 - June 2, 2010, Paris, France",

publisher = "Institute of Electrical and Electronics Engineers",

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Meijer, M, Pineda de Gyvez, J, Kup, B, Uden, van, B, Bastiaansen, P, Lammers, M & Vertregt, M 2010, A forward body bias generator for digital CMOS circuits with supply voltage scaling. in Proceedings of the 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 30 - June 2, 2010, Paris, France. Institute of Electrical and Electronics Engineers, Piscataway, pp. 2482-2485. https://doi.org/10.1109/ISCAS.2010.5537129

A forward body bias generator for digital CMOS circuits with supply voltage scaling. / Meijer, M.; Pineda de Gyvez, J.; Kup, B. et al.
Proceedings of the 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 30 - June 2, 2010, Paris, France. Piscataway: Institute of Electrical and Electronics Engineers, 2010. p. 2482-2485.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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N2 - We propose a new fully-integrated forward body bias (FBB) generator that holds its voltage constant relative to the (scalable) power supply of a digital IP. The generator is modular and can drive distinct digital IP block sizes in multiples of up to 1mm2. The design has been implemented in 90nm low-power CMOS. Our basic unit for driving digital IP blocks up to 1mm2 occupies a silicon area of 0.03mm2 only. The generator completes a 500mV FBB voltage step within 4µs. The bandwidth of the design is 570kHz. The active current of the FBB generator alone is about 177µA for a nominal process, 1.2V supply and 85°C. The standby current is as low as 72nA at 27°C.

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BT - Proceedings of the 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 30 - June 2, 2010, Paris, France

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Meijer M, Pineda de Gyvez J, Kup B, Uden, van B, Bastiaansen P, Lammers M et al. A forward body bias generator for digital CMOS circuits with supply voltage scaling. In Proceedings of the 2010 IEEE International Symposium on Circuits and Systems (ISCAS), May 30 - June 2, 2010, Paris, France. Piscataway: Institute of Electrical and Electronics Engineers. 2010. p. 2482-2485 doi: 10.1109/ISCAS.2010.5537129

A forward body bias generator for digital CMOS circuits with supply voltage scaling

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