A formal model of lower system layers

J. Schmaltz

    Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

    5 Citations (Scopus)

    Abstract

    We present a formal model of the bit transmission between registers with arbitrary clock periods. Our model considers precise timing parameters, as well as metastability. We formally define the behavior of registers over time. From that definition, we prove, under certain conditions, that data are properly transmitted. We discuss how to incorporate the model in a purely digital model. The hypotheses of our main theorem define conditions that must be satisfied by the purely digital part of the system to preserve correctness.
    Original languageEnglish
    Title of host publicationFormal Methods in Computer-Aided Design (6th International Conference, FMCAD'06, San Jose CA, USA, November 12-16, 2006. Proceedings)
    PublisherIEEE Computer Society
    Pages191-192
    ISBN (Print)0-7695-2707-8
    DOIs
    Publication statusPublished - 2006

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