A formal model of clock domain crossing and automated verification of time-triggered hardware

J. Schmaltz

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

Original language	English
Title of host publication	Formal Methods in Computer-Aided Design (7th International Conference, FMCAD'07, Austin TX, USA, November 11-14, 2007. Proceedings)
Publisher	IEEE Computer Society
Pages	223-230
DOIs	https://doi.org/10.1109/FMCAD.2007.2
Publication status	Published - 2007

Access to Document

@inproceedings{d0f53dc73eb64930b38f4f5e0c7e243b,

title = "A formal model of clock domain crossing and automated verification of time-triggered hardware",

author = "J. Schmaltz",

year = "2007",

doi = "10.1109/FMCAD.2007.2",

language = "English",

pages = "223--230",

booktitle = "Formal Methods in Computer-Aided Design (7th International Conference, FMCAD'07, Austin TX, USA, November 11-14, 2007. Proceedings)",

publisher = "IEEE Computer Society",

address = "United States",

}

A formal model of clock domain crossing and automated verification of time-triggered hardware. / Schmaltz, J.
Formal Methods in Computer-Aided Design (7th International Conference, FMCAD'07, Austin TX, USA, November 11-14, 2007. Proceedings). IEEE Computer Society, 2007. p. 223-230.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A formal model of clock domain crossing and automated verification of time-triggered hardware

AU - Schmaltz, J.

PY - 2007

Y1 - 2007

UR - http://doi.ieeecomputersociety.org/10.1109/FMCAD.2007.2

U2 - 10.1109/FMCAD.2007.2

DO - 10.1109/FMCAD.2007.2

M3 - Conference contribution

SP - 223

EP - 230

BT - Formal Methods in Computer-Aided Design (7th International Conference, FMCAD'07, Austin TX, USA, November 11-14, 2007. Proceedings)

PB - IEEE Computer Society

ER -