A flexible bottom-up approach for layout generation

M.L.P. Lierop, van

doi:10.1016/0167-9260(85)90054-9

A flexible bottom-up approach for layout generation

M.L.P. Lierop, van

Research output: Contribution to journal › Article › Academic › peer-review

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Abstract

The subject of this paper is an algorithm generating topological layouts for VLSI-circuits that are specified by means of programs. A topological layout, which is both a metric-free and a material-free layout, is an intermediate step in the process of converting a program into a silicon chip. The algorithm described in this paper is based upon a bottom-up approach, while lazy evaluation, constituted by the postponement of the construction of some connections, guarantees a flexible connecting to different environments.

Original language	English
Pages (from-to)	49-59
Number of pages	11
Journal	Integration : the VLSI Journal
Volume	3
Issue number	1
DOIs	https://doi.org/10.1016/0167-9260(85)90054-9
Publication status	Published - 1985

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@article{27667b2382c1487685175ff5d1988daf,

title = "A flexible bottom-up approach for layout generation",

abstract = "The subject of this paper is an algorithm generating topological layouts for VLSI-circuits that are specified by means of programs. A topological layout, which is both a metric-free and a material-free layout, is an intermediate step in the process of converting a program into a silicon chip. The algorithm described in this paper is based upon a bottom-up approach, while lazy evaluation, constituted by the postponement of the construction of some connections, guarantees a flexible connecting to different environments.",

author = "\{Lierop, van\}, M.L.P.",

year = "1985",

doi = "10.1016/0167-9260(85)90054-9",

language = "English",

volume = "3",

pages = "49--59",

journal = "Integration : the VLSI Journal",

issn = "0167-9260",

publisher = "Elsevier B.V.",

number = "1",

}

TY - JOUR

T1 - A flexible bottom-up approach for layout generation

AU - Lierop, van, M.L.P.

PY - 1985

Y1 - 1985

N2 - The subject of this paper is an algorithm generating topological layouts for VLSI-circuits that are specified by means of programs. A topological layout, which is both a metric-free and a material-free layout, is an intermediate step in the process of converting a program into a silicon chip. The algorithm described in this paper is based upon a bottom-up approach, while lazy evaluation, constituted by the postponement of the construction of some connections, guarantees a flexible connecting to different environments.

AB - The subject of this paper is an algorithm generating topological layouts for VLSI-circuits that are specified by means of programs. A topological layout, which is both a metric-free and a material-free layout, is an intermediate step in the process of converting a program into a silicon chip. The algorithm described in this paper is based upon a bottom-up approach, while lazy evaluation, constituted by the postponement of the construction of some connections, guarantees a flexible connecting to different environments.

U2 - 10.1016/0167-9260(85)90054-9

DO - 10.1016/0167-9260(85)90054-9

M3 - Article

SN - 0167-9260

VL - 3

SP - 49

EP - 59

JO - Integration : the VLSI Journal

JF - Integration : the VLSI Journal

IS - 1

ER -

A flexible bottom-up approach for layout generation

Abstract

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