A First-Order Continuous-Time Noise-Shaping SAR ADC with Duty-Cycled Integrator

Hanyue Li; Yuting Shen; Eugenio Cantatore; Pieter Harpe

doi:10.1109/VLSITechnologyandCir46769.2022.9830373

A First-Order Continuous-Time Noise-Shaping SAR ADC with Duty-Cycled Integrator

Hanyue Li
, Yuting Shen
, Eugenio Cantatore
, Pieter Harpe

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

16 Citations (Scopus)

238 Downloads (Pure)

Abstract

This paper presents the first continuous-time (CT) noise-shaping SAR (NS-SAR) ADC. Different from the prior discrete-time (DT) NS-SAR ADCs in literature, this ADC utilizes a CT Gm-C integrator to realize an inherent anti-aliasing function. To cope with the timing conflict between the DT-operated SAR ADC and the CT integrator, the sampling switch of the SAR ADC is removed, and the integrator is duty-cycled. Fabricated in 65 nm CMOS, the prototype achieves 77 dB peak SNDR within 62.5 kHz bandwidth while consuming 13.5 W, and it provides 15 dB anti-aliasing in the alias band.

Original language	English
Title of host publication	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Publisher	Institute of Electrical and Electronics Engineers
Pages	58-59
Number of pages	2
ISBN (Electronic)	9781665497725
DOIs	https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830373
Publication status	Published - 2022
Event	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States Duration: 12 Jun 2022 → 17 Jun 2022

Conference

Conference	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Country/Territory	United States
City	Honolulu
Period	12/06/22 → 17/06/22

Bibliographical note

Funding Information:
Acknowledgements This work is supported by the Dutch Research Council (NWO) under Project 16594. The authors would like to thank Yijing Zhang and Chenming Zhang for their helpful discussions.

Funding

Acknowledgements This work is supported by the Dutch Research Council (NWO) under Project 16594. The authors would like to thank Yijing Zhang and Chenming Zhang for their helpful discussions.

Keywords

anti-aliasing
continuous time
current steering
duty-cycled integrator
noise-shaping SAR ADC

Access to Document

10.1109/VLSITechnologyandCir46769.2022.9830373

202206 VLSI paperFinal author version , 468 KBLicence: Unspecified

Cite this

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title = "A First-Order Continuous-Time Noise-Shaping SAR ADC with Duty-Cycled Integrator",

abstract = "This paper presents the first continuous-time (CT) noise-shaping SAR (NS-SAR) ADC. Different from the prior discrete-time (DT) NS-SAR ADCs in literature, this ADC utilizes a CT Gm-C integrator to realize an inherent anti-aliasing function. To cope with the timing conflict between the DT-operated SAR ADC and the CT integrator, the sampling switch of the SAR ADC is removed, and the integrator is duty-cycled. Fabricated in 65 nm CMOS, the prototype achieves 77 dB peak SNDR within 62.5 kHz bandwidth while consuming 13.5 W, and it provides 15 dB anti-aliasing in the alias band.",

keywords = "anti-aliasing, continuous time, current steering, duty-cycled integrator, noise-shaping SAR ADC",

author = "Hanyue Li and Yuting Shen and Eugenio Cantatore and Pieter Harpe",

note = "Funding Information: Acknowledgements This work is supported by the Dutch Research Council (NWO) under Project 16594. The authors would like to thank Yijing Zhang and Chenming Zhang for their helpful discussions. ; 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 ; Conference date: 12-06-2022 Through 17-06-2022",

year = "2022",

doi = "10.1109/VLSITechnologyandCir46769.2022.9830373",

language = "English",

pages = "58--59",

booktitle = "2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022",

publisher = "Institute of Electrical and Electronics Engineers",

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Li, H, Shen, Y, Cantatore, E & Harpe, P 2022, A First-Order Continuous-Time Noise-Shaping SAR ADC with Duty-Cycled Integrator. in 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022., 9830373, Institute of Electrical and Electronics Engineers, pp. 58-59, 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022, Honolulu, United States, 12/06/22. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830373

A First-Order Continuous-Time Noise-Shaping SAR ADC with Duty-Cycled Integrator. / Li, Hanyue; Shen, Yuting; Cantatore, Eugenio et al.
2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers, 2022. p. 58-59 9830373.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

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AU - Li, Hanyue

AU - Shen, Yuting

AU - Cantatore, Eugenio

AU - Harpe, Pieter

N1 - Funding Information: Acknowledgements This work is supported by the Dutch Research Council (NWO) under Project 16594. The authors would like to thank Yijing Zhang and Chenming Zhang for their helpful discussions.

PY - 2022

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N2 - This paper presents the first continuous-time (CT) noise-shaping SAR (NS-SAR) ADC. Different from the prior discrete-time (DT) NS-SAR ADCs in literature, this ADC utilizes a CT Gm-C integrator to realize an inherent anti-aliasing function. To cope with the timing conflict between the DT-operated SAR ADC and the CT integrator, the sampling switch of the SAR ADC is removed, and the integrator is duty-cycled. Fabricated in 65 nm CMOS, the prototype achieves 77 dB peak SNDR within 62.5 kHz bandwidth while consuming 13.5 W, and it provides 15 dB anti-aliasing in the alias band.

AB - This paper presents the first continuous-time (CT) noise-shaping SAR (NS-SAR) ADC. Different from the prior discrete-time (DT) NS-SAR ADCs in literature, this ADC utilizes a CT Gm-C integrator to realize an inherent anti-aliasing function. To cope with the timing conflict between the DT-operated SAR ADC and the CT integrator, the sampling switch of the SAR ADC is removed, and the integrator is duty-cycled. Fabricated in 65 nm CMOS, the prototype achieves 77 dB peak SNDR within 62.5 kHz bandwidth while consuming 13.5 W, and it provides 15 dB anti-aliasing in the alias band.

KW - anti-aliasing

KW - continuous time

KW - current steering

KW - duty-cycled integrator

KW - noise-shaping SAR ADC

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M3 - Conference contribution

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EP - 59

BT - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022

PB - Institute of Electrical and Electronics Engineers

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Y2 - 12 June 2022 through 17 June 2022

ER -

A First-Order Continuous-Time Noise-Shaping SAR ADC with Duty-Cycled Integrator

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Keywords

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