A DLL-based Poly-phase Sample for Sigma-Delta ADC

Due to their simple and cost-effective implementation Sigma-Delta ADCs are preferred converters in many low frequency applications. However, despite the high demand, there are still only a few designs that achieve high performance for bandwidths in the MHz range and above. A main difficulty in utilizing Sigma-Delta converters for higher frequency bandwidths comes from the basics of their operation, namely from the need for a high oversampling ratio. This high oversampling ratio is usually obtained by a high frequency sampling operation and high quality decision switches. In Sigma-Delta converters, those switches operate on weak high-speed signals and can introduce performance degrading effects like asymmetry, metastability or excessive loop delays. In this paper an alternative implementation of the sampling circuit as suggested in [1] is described. Instead of a single phase clock, the sampler generates N equally spaced clock phases that are synchronized to an external reference clock with the help of a Delay Lock Loop (DLL). This poly-phase sampling allows for a high overall oversampling ratio with a much lower effective sampling speed. In this way the sampling operation is parallelized and the requirements towards the speed and accuracy of the individual decision switches are significantly decreased. In this paper the implementation of an eight-phase, 1GHz poly-phase sampler is shown. The circuit level design requirements for a single delay element, chain of delay elements and a complete DLL are discussed and the basic tradeoffs are described.