A direct-sampling multi-channel receiver for DOCSIS 3.0 in 65nm CMOS

E. Janssen; K. Doris; A. Zanikopoulos; G. Weide, van der; M. Vertregt; O. Jamin; F. Courtois; N. Blard; M. Kristen; S. Bertrand; F. Riviere; F. Deforeit; G. Blanc; Y. Penning; F. Lefebvre; D. Viguier; M. Dubois; V. Vrignaud; C. Cazettes; L. Schaller; G. Jenvrin

A direct-sampling multi-channel receiver for DOCSIS 3.0 in 65nm CMOS

E. Janssen, K. Doris, A. Zanikopoulos, G. Weide, van der, M. Vertregt, O. Jamin, F. Courtois, N. Blard, M. Kristen, S. Bertrand, F. Riviere, F. Deforeit, G. Blanc, Y. Penning, F. Lefebvre, D. Viguier, M. Dubois, V. Vrignaud, C. Cazettes, L. SchallerG. Jenvrin

Integrated Circuits

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

12 Citations (Scopus)

Abstract

This paper presents a fully integrated direct sampling receiver for DOCSIS 3.0, consisting of a time-interleaved ADC, a digital multi-channel selection filter, and a PLL. The receiver can simultaneously receive 4 streams from arbitrary RF frequencies between 48 and 1002MHz and output these in a 13.5MS/s digital IQ format or at a low-IF through integrated DACs. It consumes 980mW from a split 1.2/1.3/1.6V supply when receiving 4 channels and occupies 16.8mm2 in 65nm CMOS.

Original language	English
Title of host publication	Proceeding of the Conference on VLSI Circuits 2011 (VLSIC), 15-17 June 2011, Kyoto
Pages	292-293
Publication status	Published - 2011
Event	2011 Symposium on VLSI Circuits (VLSIC 2011) - Rihga Royal Hotel, Kyoto, Japan Duration: 14 Jun 2011 → 17 Jun 2011 http://www.vlsisymposium.org/Past/11web/

Conference

Conference	2011 Symposium on VLSI Circuits (VLSIC 2011)
Abbreviated title	VLSIC 2011
Country/Territory	Japan
City	Kyoto
Period	14/06/11 → 17/06/11
Other	Symposium held jointly with the 2011 Symposium on VLSI Technology
Internet address	http://www.vlsisymposium.org/Past/11web/

Cite this

Janssen, E., Doris, K., Zanikopoulos, A., Weide, van der, G., Vertregt, M., Jamin, O., Courtois, F., Blard, N., Kristen, M., Bertrand, S., Riviere, F., Deforeit, F., Blanc, G., Penning, Y., Lefebvre, F., Viguier, D., Dubois, M., Vrignaud, V., Cazettes, C., ... Jenvrin, G. (2011). A direct-sampling multi-channel receiver for DOCSIS 3.0 in 65nm CMOS. In Proceeding of the Conference on VLSI Circuits 2011 (VLSIC), 15-17 June 2011, Kyoto (pp. 292-293)

@inproceedings{7d14e04e8509466290624ae10f9bc92f,

title = "A direct-sampling multi-channel receiver for DOCSIS 3.0 in 65nm CMOS",

abstract = "This paper presents a fully integrated direct sampling receiver for DOCSIS 3.0, consisting of a time-interleaved ADC, a digital multi-channel selection filter, and a PLL. The receiver can simultaneously receive 4 streams from arbitrary RF frequencies between 48 and 1002MHz and output these in a 13.5MS/s digital IQ format or at a low-IF through integrated DACs. It consumes 980mW from a split 1.2/1.3/1.6V supply when receiving 4 channels and occupies 16.8mm2 in 65nm CMOS.",

author = "E. Janssen and K. Doris and A. Zanikopoulos and {Weide, van der}, G. and M. Vertregt and O. Jamin and F. Courtois and N. Blard and M. Kristen and S. Bertrand and F. Riviere and F. Deforeit and G. Blanc and Y. Penning and F. Lefebvre and D. Viguier and M. Dubois and V. Vrignaud and C. Cazettes and L. Schaller and G. Jenvrin",

year = "2011",

language = "English",

pages = "292--293",

booktitle = "Proceeding of the Conference on VLSI Circuits 2011 (VLSIC), 15-17 June 2011, Kyoto",

note = "2011 Symposium on VLSI Circuits (VLSIC 2011), VLSIC 2011 ; Conference date: 14-06-2011 Through 17-06-2011",

url = "http://www.vlsisymposium.org/Past/11web/",

}

Janssen, E, Doris, K, Zanikopoulos, A, Weide, van der, G, Vertregt, M, Jamin, O, Courtois, F, Blard, N, Kristen, M, Bertrand, S, Riviere, F, Deforeit, F, Blanc, G, Penning, Y, Lefebvre, F, Viguier, D, Dubois, M, Vrignaud, V, Cazettes, C, Schaller, L & Jenvrin, G 2011, A direct-sampling multi-channel receiver for DOCSIS 3.0 in 65nm CMOS. in Proceeding of the Conference on VLSI Circuits 2011 (VLSIC), 15-17 June 2011, Kyoto. pp. 292-293, 2011 Symposium on VLSI Circuits (VLSIC 2011), Kyoto, Japan, 14/06/11.

TY - GEN

T1 - A direct-sampling multi-channel receiver for DOCSIS 3.0 in 65nm CMOS

AU - Janssen, E.

AU - Doris, K.

AU - Zanikopoulos, A.

AU - Weide, van der, G.

AU - Vertregt, M.

AU - Jamin, O.

AU - Courtois, F.

AU - Blard, N.

AU - Kristen, M.

AU - Bertrand, S.

AU - Riviere, F.

AU - Deforeit, F.

AU - Blanc, G.

AU - Penning, Y.

AU - Lefebvre, F.

AU - Viguier, D.

AU - Dubois, M.

AU - Vrignaud, V.

AU - Cazettes, C.

AU - Schaller, L.

AU - Jenvrin, G.

PY - 2011

Y1 - 2011

N2 - This paper presents a fully integrated direct sampling receiver for DOCSIS 3.0, consisting of a time-interleaved ADC, a digital multi-channel selection filter, and a PLL. The receiver can simultaneously receive 4 streams from arbitrary RF frequencies between 48 and 1002MHz and output these in a 13.5MS/s digital IQ format or at a low-IF through integrated DACs. It consumes 980mW from a split 1.2/1.3/1.6V supply when receiving 4 channels and occupies 16.8mm2 in 65nm CMOS.

AB - This paper presents a fully integrated direct sampling receiver for DOCSIS 3.0, consisting of a time-interleaved ADC, a digital multi-channel selection filter, and a PLL. The receiver can simultaneously receive 4 streams from arbitrary RF frequencies between 48 and 1002MHz and output these in a 13.5MS/s digital IQ format or at a low-IF through integrated DACs. It consumes 980mW from a split 1.2/1.3/1.6V supply when receiving 4 channels and occupies 16.8mm2 in 65nm CMOS.

M3 - Conference contribution

SP - 292

EP - 293

BT - Proceeding of the Conference on VLSI Circuits 2011 (VLSIC), 15-17 June 2011, Kyoto

T2 - 2011 Symposium on VLSI Circuits (VLSIC 2011)

Y2 - 14 June 2011 through 17 June 2011

ER -

A direct-sampling multi-channel receiver for DOCSIS 3.0 in 65nm CMOS

Abstract

Conference

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