A direct-sampling multi-channel receiver for DOCSIS 3.0 in 65nm CMOS

E. Janssen, K. Doris, A. Zanikopoulos, G. Weide, van der, M. Vertregt, O. Jamin, F. Courtois, N. Blard, M. Kristen, S. Bertrand, F. Riviere, F. Deforeit, G. Blanc, Y. Penning, F. Lefebvre, D. Viguier, M. Dubois, V. Vrignaud, C. Cazettes, L. SchallerG. Jenvrin

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

12 Citations (Scopus)


This paper presents a fully integrated direct sampling receiver for DOCSIS 3.0, consisting of a time-interleaved ADC, a digital multi-channel selection filter, and a PLL. The receiver can simultaneously receive 4 streams from arbitrary RF frequencies between 48 and 1002MHz and output these in a 13.5MS/s digital IQ format or at a low-IF through integrated DACs. It consumes 980mW from a split 1.2/1.3/1.6V supply when receiving 4 channels and occupies 16.8mm2 in 65nm CMOS.
Original languageEnglish
Title of host publicationProceeding of the Conference on VLSI Circuits 2011 (VLSIC), 15-17 June 2011, Kyoto
Publication statusPublished - 2011
Event2011 Symposium on VLSI Circuits (VLSIC 2011) - Rihga Royal Hotel, Kyoto, Japan
Duration: 14 Jun 201117 Jun 2011


Conference2011 Symposium on VLSI Circuits (VLSIC 2011)
Abbreviated titleVLSIC 2011
OtherSymposium held jointly with the 2011 Symposium on VLSI Technology
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