A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS

B. Wang; Y.-H. Liu; P.J.A. Harpe; J.H.C. Heuvel, van den; B. Liu; H. Gao; R.B. Staszewski

doi:10.1109/ISCAS.2015.7169140

A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS

B. Wang
, Y.-H. Liu
, P.J.A. Harpe
, J.H.C. Heuvel, van den
, B. Liu
, H. Gao
, R.B. Staszewski

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

14 Citations (Scopus)

1 Downloads (Pure)

Abstract

In this paper, a digital time skew calibration technique for time-interleaved (TI) ADCs is presented. The time skew calibration for TI-ADCs in analog domain suffers from limited correction accuracy and additional jitter. And the proposed digital time skew calibration method estimates the polarity of the time skew through correlation of adjacent channels and corrects the time error by adopting adaptive fractional delay filters iteratively. Simulation results show that, in a 4-channel 1GS/s 12-bit TI-ADC system, the SFDR can be improved to 78dB by 5-order FIR filters within a calibration range of [-0.005/fs, 0.005/fs].

Original language	English
Title of host publication	Proceedings of the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May 24-27 2015, Lisbon, Portugal
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	2289-2292
ISBN (Print)	978-1-4799-8391-9
DOIs	https://doi.org/10.1109/ISCAS.2015.7169140
Publication status	Published - 2015
Event	2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015) - Lisbon, Portugal, Lisbon, Portugal Duration: 24 May 2015 → 27 May 2015 http://www.iscas2015.org/

Conference

Conference	2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015)
Abbreviated title	ISCAS 2015
Country/Territory	Portugal
City	Lisbon
Period	24/05/15 → 27/05/15
Internet address	http://www.iscas2015.org/

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10.1109/ISCAS.2015.7169140

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Wang, B., Liu, Y.-H., Harpe, P. J. A., Heuvel, van den, J. H. C., Liu, B., Gao, H., & Staszewski, R. B. (2015). A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS. In Proceedings of the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May 24-27 2015, Lisbon, Portugal (pp. 2289-2292). Article C2P-V.3 Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISCAS.2015.7169140

@inproceedings{8f048eb10c1147f4ad3c49018f35a848,

title = "A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS",

abstract = "In this paper, a digital time skew calibration technique for time-interleaved (TI) ADCs is presented. The time skew calibration for TI-ADCs in analog domain suffers from limited correction accuracy and additional jitter. And the proposed digital time skew calibration method estimates the polarity of the time skew through correlation of adjacent channels and corrects the time error by adopting adaptive fractional delay filters iteratively. Simulation results show that, in a 4-channel 1GS/s 12-bit TI-ADC system, the SFDR can be improved to 78dB by 5-order FIR filters within a calibration range of [-0.005/fs, 0.005/fs].",

author = "B. Wang and Y.-H. Liu and P.J.A. Harpe and \{Heuvel, van den\}, J.H.C. and B. Liu and H. Gao and R.B. Staszewski",

year = "2015",

doi = "10.1109/ISCAS.2015.7169140",

language = "English",

isbn = "978-1-4799-8391-9",

pages = "2289--2292",

booktitle = "Proceedings of the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May 24-27 2015, Lisbon, Portugal",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015), ISCAS 2015 ; Conference date: 24-05-2015 Through 27-05-2015",

url = "http://www.iscas2015.org/",

}

Wang, B, Liu, Y-H , Harpe, PJA, Heuvel, van den, JHC, Liu, B, Gao, H & Staszewski, RB 2015, A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS. in Proceedings of the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May 24-27 2015, Lisbon, Portugal., C2P-V.3, Institute of Electrical and Electronics Engineers, Piscataway, pp. 2289-2292, 2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015), Lisbon, Portugal, 24/05/15. https://doi.org/10.1109/ISCAS.2015.7169140

A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS. / Wang, B.; Liu, Y.-H.; Harpe, P.J.A. et al.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May 24-27 2015, Lisbon, Portugal. Piscataway: Institute of Electrical and Electronics Engineers, 2015. p. 2289-2292 C2P-V.3.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS

AU - Wang, B.

AU - Liu, Y.-H.

AU - Harpe, P.J.A.

AU - Heuvel, van den, J.H.C.

AU - Liu, B.

AU - Gao, H.

AU - Staszewski, R.B.

PY - 2015

Y1 - 2015

N2 - In this paper, a digital time skew calibration technique for time-interleaved (TI) ADCs is presented. The time skew calibration for TI-ADCs in analog domain suffers from limited correction accuracy and additional jitter. And the proposed digital time skew calibration method estimates the polarity of the time skew through correlation of adjacent channels and corrects the time error by adopting adaptive fractional delay filters iteratively. Simulation results show that, in a 4-channel 1GS/s 12-bit TI-ADC system, the SFDR can be improved to 78dB by 5-order FIR filters within a calibration range of [-0.005/fs, 0.005/fs].

AB - In this paper, a digital time skew calibration technique for time-interleaved (TI) ADCs is presented. The time skew calibration for TI-ADCs in analog domain suffers from limited correction accuracy and additional jitter. And the proposed digital time skew calibration method estimates the polarity of the time skew through correlation of adjacent channels and corrects the time error by adopting adaptive fractional delay filters iteratively. Simulation results show that, in a 4-channel 1GS/s 12-bit TI-ADC system, the SFDR can be improved to 78dB by 5-order FIR filters within a calibration range of [-0.005/fs, 0.005/fs].

U2 - 10.1109/ISCAS.2015.7169140

DO - 10.1109/ISCAS.2015.7169140

M3 - Conference contribution

SN - 978-1-4799-8391-9

SP - 2289

EP - 2292

BT - Proceedings of the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May 24-27 2015, Lisbon, Portugal

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015)

Y2 - 24 May 2015 through 27 May 2015

ER -

Wang B, Liu YH , Harpe PJA, Heuvel, van den JHC, Liu B, Gao H et al. A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS. In Proceedings of the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May 24-27 2015, Lisbon, Portugal. Piscataway: Institute of Electrical and Electronics Engineers. 2015. p. 2289-2292. C2P-V.3 doi: 10.1109/ISCAS.2015.7169140

A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS

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