A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS

B. Wang, Y.-H. Liu, P.J.A. Harpe, J.H.C. Heuvel, van den, B. Liu, H. Gao, R.B. Staszewski

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Abstract

In this paper, a digital time skew calibration technique for time-interleaved (TI) ADCs is presented. The time skew calibration for TI-ADCs in analog domain suffers from limited correction accuracy and additional jitter. And the proposed digital time skew calibration method estimates the polarity of the time skew through correlation of adjacent channels and corrects the time error by adopting adaptive fractional delay filters iteratively. Simulation results show that, in a 4-channel 1GS/s 12-bit TI-ADC system, the SFDR can be improved to 78dB by 5-order FIR filters within a calibration range of [-0.005/fs, 0.005/fs].
Original languageEnglish
Title of host publicationProceedings of the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May 24-27 2015, Lisbon, Portugal
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Pages2289-2292
ISBN (Print)978-1-4799-8391-9
DOIs
Publication statusPublished - 2015
Event2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015) - Lisbon, Portugal
Duration: 24 May 201527 May 2015
http://www.iscas2015.org/

Conference

Conference2015 IEEE International Symposium on Circuits and Systems (ISCAS 2015)
Abbreviated titleISCAS 2015
CountryPortugal
CityLisbon
Period24/05/1527/05/15
Internet address

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Cite this

Wang, B., Liu, Y-H., Harpe, P. J. A., Heuvel, van den, J. H. C., Liu, B., Gao, H., & Staszewski, R. B. (2015). A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS. In Proceedings of the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May 24-27 2015, Lisbon, Portugal (pp. 2289-2292). [C2P-V.3] Piscataway: Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/ISCAS.2015.7169140