A DfT architecture for 3D-SICs based on a standardizable die wrapper

Erik Jan Marinissen, Chun Chuan Chi, Mario Konijnenburg, Jouke Verbree

Research output: Contribution to journalReview articlepeer-review

34 Citations (Scopus)
34 Downloads (Pure)


Process technology developments enable the creation of three-dimensional stacked ICs (3D-SICs) interconnected by means of Through-Silicon Vias (TSVs). This paper presents a 3D Design-for-Test (DfT) architecture for such 3D-SICs that allows pre-bond die testing as well as mid-bond and post-bond stack testing. The architecture enables a modular test approach, in which the various dies, their embedded IP cores, the inter-die TSV-based interconnects, and the external I/Os can be tested as separate units, which allows flexible optimization of the 3D-SIC test flow and provides yield monitoring and first-order fault diagnosis. The architecture builds on and reuses existing DfT hardware at the core, die, and product level. Its main new component is a die-level wrapper, which can be based on either IEEE Std 1149.1 or IEEE Std 1500. The paper presents a conceptual overview of the architecture, as well as implementation aspects. Experimental results show that the implementation costs are negligible for medium to large dies.

Original languageEnglish
Pages (from-to)73-92
Number of pages20
JournalJournal of Electronic Testing : Theory and Applications
Issue number1
Publication statusPublished - 1 Feb 2012
Externally publishedYes


  • 3D stacked ICs
  • Design-for-test
  • IEEE 1149.1
  • IEEE 1500
  • Manufacturing test
  • Standardization
  • Test access mechanism
  • Through-silicon via
  • Wrapper


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