A detailed GPU cache model based on reuse distance theory

C. Nugteren, G.J.W. Braak, van den, H. Corporaal, H.E. Bal

Research output: Chapter in Book/Report/Conference proceedingConference contributionAcademicpeer-review

84 Citations (Scopus)
196 Downloads (Pure)


As modern GPUs rely partly on their on-chip memories to counter the imminent off-chip memory wall, the efficient use of their caches has become important for performance and energy. However, optimising cache locality systematically requires insight into and prediction of cache behaviour. On sequential processors, stack distance or reuse distance theory is a well-known means to model cache behaviour. However, it is not straightforward to apply this theory to GPUs, mainly because of the parallel execution model and fine-grained multi-threading. This work extends reuse distance to GPUs by modelling: 1) the GPU’s hierarchy of threads, warps, threadblocks, and sets of active threads, 2) conditional and non-uniform latencies, 3) cache associativity, 4) miss-status holding-registers, and 5) warp divergence. We implement the model in C++ and extend the Ocelot GPU emulator to extract lists of memory addresses. We compare our model with measured cache miss rates for the Parboil and PolyBench/GPU benchmark suites, showing a mean absolute error of 6% and 8% for two cache configurations. We show that our model is faster and even more accurate compared to the GPGPU-Sim simulator.
Original languageEnglish
Title of host publicationProceedings of the IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), 15-19 February 2014, Orlando, Florida
Place of PublicationPiscataway
PublisherInstitute of Electrical and Electronics Engineers
Publication statusPublished - 2014
Eventconference; High Performance Computer Architecture (HPCA); 2014-02-15; 2014-02-19 -
Duration: 15 Feb 201419 Feb 2014


Conferenceconference; High Performance Computer Architecture (HPCA); 2014-02-15; 2014-02-19
OtherHigh Performance Computer Architecture (HPCA)


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