This poster presents a design methodology for wideband continuous-time MASH ΣΔ ADCs that takes into account one clock cycle delay for each comparator. This enables the design of high-speed wide-band MASH ΣΔ ADCs, with high sampling rate and low OSR. The purpose of this research is to synthesize a continuous-time MASH ΣΔ ADC architecture suitable for wideband medium resolution ADC applications. The synthesis starts form a discrete-time MASH ΣΔ ADC architecture, with one clock cycle delay modelled for each comparator . Then, discrete-time to continuous-time transformation technique similar as  is applied to determine the design parameters of the continuous-time MASH ΣΔ ADC architecture. Extra coefficients are introduced to provide the required additional degrees of freedom. Subsequently, a wide-band continuous-time MASH ΣΔ ADC architecture is synthesized, which is robust against loop delay variations. Extensive simulation results show the robustness and the advantages of the proposed methodology. It delivers a 9-level 1-1-1 wideband MASH ΣΔ ADC topology with 3.25 times larger signal BW when compared to the traditional approach with the same total loop delay and SNDR target. Compared to the state-of-the-art , it enlarges the signal BW by a factor of 2 through enabling 2 times higher sampling frequency without losing DR performance. Moreover, it facilitates the design and simulation procedures. All these properties make the proposed methodology very useful for designing wide-band medium resolution ΣΔ ADCs for high performance mixed-signal applications.
|Publication status||Published - 22 Mar 2016|
|Event||ICT.OPEN 2016 - De Flint, Amersfoort, Netherlands|
Duration: 22 Mar 2016 → 23 Mar 2016
|Period||22/03/16 → 23/03/16|
|Other||The Interface for Dutch ICT-Research|