A Design Methodology for Wide-Band Continuous-Time MASH ΣΔ ADC Architectures

C. Zhang, L.J. Breems, G.I. Radulov, J.A. Hegt, A.H.M. van Roermund

Research output: Contribution to conferencePoster


This poster presents a design methodology for wideband continuous-time MASH ΣΔ ADCs that takes into account one clock cycle delay for each comparator. This enables the design of high-speed wide-band MASH ΣΔ ADCs, with high sampling rate and low OSR. The purpose of this research is to synthesize a continuous-time MASH ΣΔ ADC architecture suitable for wideband medium resolution ADC applications. The synthesis starts form a discrete-time MASH ΣΔ ADC architecture, with one clock cycle delay modelled for each comparator [1]. Then, discrete-time to continuous-time transformation technique similar as [2] is applied to determine the design parameters of the continuous-time MASH ΣΔ ADC architecture. Extra coefficients are introduced to provide the required additional degrees of freedom. Subsequently, a wide-band continuous-time MASH ΣΔ ADC architecture is synthesized, which is robust against loop delay variations. Extensive simulation results show the robustness and the advantages of the proposed methodology. It delivers a 9-level 1-1-1 wideband MASH ΣΔ ADC topology with 3.25 times larger signal BW when compared to the traditional approach with the same total loop delay and SNDR target. Compared to the state-of-the-art [3], it enlarges the signal BW by a factor of 2 through enabling 2 times higher sampling frequency without losing DR performance. Moreover, it facilitates the design and simulation procedures. All these properties make the proposed methodology very useful for designing wide-band medium resolution ΣΔ ADCs for high performance mixed-signal applications.
Original languageEnglish
Publication statusPublished - 22 Mar 2016
EventICT.OPEN 2016 - De Flint, Amersfoort, Netherlands
Duration: 22 Mar 201623 Mar 2016


ConferenceICT.OPEN 2016
OtherThe Interface for Dutch ICT-Research
Internet address


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