Abstract
A serial-parallel multiplier is developed systematically from functional specification to circuit implementation. First, a functional program is derived and, second, a parallel program for a systolic computation is constructed. The parallel program is derived from the functional program. Both synchronous and asynchronous circuit implementations for the parallel program are discussed. The latter implementation has a pipeline structure with bounded response time.
| Original language | English |
|---|---|
| Pages (from-to) | 201-215 |
| Journal | Science of Computer Programming |
| Volume | 15 |
| Issue number | 2-3 |
| DOIs | |
| Publication status | Published - 1990 |
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