A compact 10-b SAR ADC with unit-length capacitors and a passive FIR filter

Pieter Harpe (Corresponding author)

Research output: Contribution to journalArticleAcademicpeer-review

4 Citations (Scopus)
118 Downloads (Pure)

Abstract

This paper presents a compact 10-b successive approximation register analog-to-digital converter (SAR ADC) in 65-nm CMOS with an integrated passive finite impulse response (FIR) filter for anti-aliasing. Conventional switched-capacitor digital-to-analog converters (DACs) are usually implemented with unit elements for the best matching performance, at the cost of increased chip area. Instead, this paper proposes a unit-length capacitor implementation, which minimizes the number of components and thus minimizes area, while also achieving good linearity (integral non-linearity of 0.39 LSB, differential non-linearity of 0.55 LSB, and SFDR of 75 dB) despite using a small LSB capacitor of 125 aF. The 10-b SAR ADC occupies only 36 × 36 µm, thanks to the small-size DAC, and by placing the ADC circuits directly under the capacitors. The ADC was tested at 10 and 30 MS/s and achieves an effective number of bits of 9.18/9.10 bit with an figure-of-merit of 4.1/4.4 fJ per conversion-step, respectively. Besides the ADC, a passive analog FIR filter is added to implement an anti-aliasing filter. The topology is based on a passive charge-sharing network and thus only consumes power for the clock phase generation and switch drivers. A 4× time-interleaved 15-tap passive FIR filter is implemented, which can realize >42 dB out-of-band rejection and 4× decimation while occupying only 53 × 90 µm. The filter and the ADC together consume 39.2µW for an output rate of 10 MS/s.

Original languageEnglish
Article number8540794
Pages (from-to)636-645
Number of pages10
JournalIEEE Journal of Solid-State Circuits
Volume54
Issue number3
DOIs
Publication statusPublished - 1 Mar 2019

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Passive filters
FIR filters
Digital to analog conversion
Capacitors
Anti-aliasing
Clocks
Switches
Topology
Networks (circuits)

Keywords

  • Analog-to-digital converter
  • FIR filter
  • Matching
  • Successive approximation register
  • Switched capacitor network

Cite this

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abstract = "This paper presents a compact 10-b successive approximation register analog-to-digital converter (SAR ADC) in 65-nm CMOS with an integrated passive finite impulse response (FIR) filter for anti-aliasing. Conventional switched-capacitor digital-to-analog converters (DACs) are usually implemented with unit elements for the best matching performance, at the cost of increased chip area. Instead, this paper proposes a unit-length capacitor implementation, which minimizes the number of components and thus minimizes area, while also achieving good linearity (integral non-linearity of 0.39 LSB, differential non-linearity of 0.55 LSB, and SFDR of 75 dB) despite using a small LSB capacitor of 125 aF. The 10-b SAR ADC occupies only 36 × 36 µm, thanks to the small-size DAC, and by placing the ADC circuits directly under the capacitors. The ADC was tested at 10 and 30 MS/s and achieves an effective number of bits of 9.18/9.10 bit with an figure-of-merit of 4.1/4.4 fJ per conversion-step, respectively. Besides the ADC, a passive analog FIR filter is added to implement an anti-aliasing filter. The topology is based on a passive charge-sharing network and thus only consumes power for the clock phase generation and switch drivers. A 4× time-interleaved 15-tap passive FIR filter is implemented, which can realize >42 dB out-of-band rejection and 4× decimation while occupying only 53 × 90 µm. The filter and the ADC together consume 39.2µW for an output rate of 10 MS/s.",
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A compact 10-b SAR ADC with unit-length capacitors and a passive FIR filter. / Harpe, Pieter (Corresponding author).

In: IEEE Journal of Solid-State Circuits, Vol. 54, No. 3, 8540794, 01.03.2019, p. 636-645.

Research output: Contribution to journalArticleAcademicpeer-review

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