A Compact 0.0054 mm2Multipurpose Analog Frontend for Ultrasound Digitizers in 40nm CMOS

Kevin Pelzers; Haoming Xin; Eugenio Cantatore; Pieter Harpe

doi:10.1109/TCSII.2022.3161867

A Compact 0.0054 mm²Multipurpose Analog Frontend for Ultrasound Digitizers in 40nm CMOS

Kevin Pelzers (Corresponding author)
, Haoming Xin
, Eugenio Cantatore
, Pieter Harpe

Research output: Contribution to journal › Article › Academic › peer-review

3 Citations (Scopus)

252 Downloads (Pure)

Abstract

This brief presents the analysis, design, and measurements of a compact analog frontend for a catheter-integrated ultrasound imaging digitizer. This frontend requires several functions, including single-ended-to-differential conversion, AC coupling, amplification, anti-aliasing, and the capability to drive the subsequent ADC. To minimize chip area and to maximize power efficiency, a 2-stage frontend was designed, where the active stages are built using self-biased inverter-based amplifiers. The measured prototype in 40nm CMOS offers a gain of up to 15dB and a bandwidth up to 20MHz, while consuming up to 162μ W from a 1.1V supply. The peak FoM of 158dB(J-1) and chip area of 0.0054mm2 are in line with state-of-the-art filters, while the proposed design includes the aforementioned extra functionalities as well.

Original language	English
Article number	9740227
Pages (from-to)	2483-2487
Number of pages	5
Journal	IEEE Transactions on Circuits and Systems II: Express Briefs
Volume	69
Issue number	5
DOIs	https://doi.org/10.1109/TCSII.2022.3161867
Publication status	Published - 1 May 2022

Bibliographical note

Funding Information:
This work was supported in part by the Position-II Project funded by the ECSEL Joint Undertaking under Grant Ecsel-783132-Position-II-2017-IA. This brief was recommended by Associate Editor J. Jiang. (Corresponding author: Kevin Pelzers.)

Funding

This work was supported in part by the Position-II Project funded by the ECSEL Joint Undertaking under Grant Ecsel-783132-Position-II-2017-IA. This brief was recommended by Associate Editor J. Jiang. (Corresponding author: Kevin Pelzers.)

Keywords

ADC driver
Analog filter
ICE
IVUS
low power
single-ended-to-differential converter
small area
ultrasound imaging

Access to Document

10.1109/TCSII.2022.3161867

pdfFinal published version, 1.14 MBLicence: TAVERNE

Cite this

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title = "A Compact 0.0054 mm2Multipurpose Analog Frontend for Ultrasound Digitizers in 40nm CMOS",

abstract = "This brief presents the analysis, design, and measurements of a compact analog frontend for a catheter-integrated ultrasound imaging digitizer. This frontend requires several functions, including single-ended-to-differential conversion, AC coupling, amplification, anti-aliasing, and the capability to drive the subsequent ADC. To minimize chip area and to maximize power efficiency, a 2-stage frontend was designed, where the active stages are built using self-biased inverter-based amplifiers. The measured prototype in 40nm CMOS offers a gain of up to 15dB and a bandwidth up to 20MHz, while consuming up to 162μ W from a 1.1V supply. The peak FoM of 158dB(J-1) and chip area of 0.0054mm2 are in line with state-of-the-art filters, while the proposed design includes the aforementioned extra functionalities as well.",

keywords = "ADC driver, Analog filter, ICE, IVUS, low power, single-ended-to-differential converter, small area, ultrasound imaging",

author = "Kevin Pelzers and Haoming Xin and Eugenio Cantatore and Pieter Harpe",

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N1 - Funding Information: This work was supported in part by the Position-II Project funded by the ECSEL Joint Undertaking under Grant Ecsel-783132-Position-II-2017-IA. This brief was recommended by Associate Editor J. Jiang. (Corresponding author: Kevin Pelzers.)

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AB - This brief presents the analysis, design, and measurements of a compact analog frontend for a catheter-integrated ultrasound imaging digitizer. This frontend requires several functions, including single-ended-to-differential conversion, AC coupling, amplification, anti-aliasing, and the capability to drive the subsequent ADC. To minimize chip area and to maximize power efficiency, a 2-stage frontend was designed, where the active stages are built using self-biased inverter-based amplifiers. The measured prototype in 40nm CMOS offers a gain of up to 15dB and a bandwidth up to 20MHz, while consuming up to 162μ W from a 1.1V supply. The peak FoM of 158dB(J-1) and chip area of 0.0054mm2 are in line with state-of-the-art filters, while the proposed design includes the aforementioned extra functionalities as well.

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