A CMOS V-I converter with 75dB SFDR and 360uW power consumption

S.F. Ouzounov, E. Roza, J.A. Hegt, G. Weide, van der, A.H.M. Roermund, van

Research output: Contribution to journalArticleAcademicpeer-review

32 Citations (Scopus)
179 Downloads (Pure)


This work describes a method for analysis of voltage-to-current converters (V-I converters or transconductors) and a novel V- I converter circuit with significantly improved linearity. The new circuit utilizes a combination of cross-coupling and local resistive feedback for a significant, simultaneous suppression of the third- and fifth-order harmonic distortion components in the transconductor characteristics. An evaluation of the optimal circuit dimensioning is shown. Simple and robust design rules are derived for the chosen operation conditions. The transistor implementation is presented and a prototype V- I converter is realized in a digital 0.18-µm CMOS technology. The measured spurious-free dynamic range is 75 dB in a frequency band of 10 MHz. The circuit occupies less than 0.02 mm2 and dissipates 360 µW.
Original languageEnglish
Pages (from-to)1527-1532
Number of pages6
JournalIEEE Journal of Solid-State Circuits
Issue number7
Publication statusPublished - 2005


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