Abstract
A circuit-design-driven tool with a hybrid design automation approach for asynchronous SAR ADCs in IoT applications is presented. To minimize the circuit design time while still being able to maintain ADC performance, the hybrid approach allocates automation and manual effort properly for each block: fully-synthesized control logic, highly-automated DAC and S&H circuit, library-based comparator and template-based layout generation. A user interface governs the automated design flow from specification and circuit implementation to layout generation. Two prototypes are generated using the proposed flow in 40nm CMOS: an 8b 32MS/s and a 12b 1MS/s SAR ADC. The measured and the simulated ADC performance are in good agreement, showing the robustness of the proposed method. At 1V supply, two chips consume 187μW and 16.7μW, achieving 30.7fJ/conversion.step and 18.1fJ/conversion.step respectively.
| Language | English |
|---|---|
| Title of host publication | Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018 |
| Publisher | Institute of Electrical and Electronics Engineers |
| Pages | 672-675 |
| Number of pages | 4 |
| Volume | 2018-January |
| ISBN (Electronic) | 9783981926316 |
| DOIs | |
| State | Published - 19 Apr 2018 |
| Event | 21st Design, Automation and Test in Europe Conference and Exhibition (DATE 2018) - Dresden, Germany Duration: 19 Mar 2018 → 23 Mar 2018 Conference number: 21 https://www.date-conference.com/date18/ |
Conference
| Conference | 21st Design, Automation and Test in Europe Conference and Exhibition (DATE 2018) |
|---|---|
| Abbreviated title | DATE 2018 |
| Country | Germany |
| City | Dresden |
| Period | 19/03/18 → 23/03/18 |
| Internet address |
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Keywords
- Design Automation
- Hybrid
- SAR ADC
Cite this
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A circuit-design-driven tool with a hybrid automation approach for SAR ADCs in IoT. / Ding, Ming; Chen, Guibin; Harpe, Pieter; Busze, Benjamin; Liu, Yao Hong; Bachmann, Christian; Philips, Kathleen; van Roermund, Arthur.
Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018. Vol. 2018-January Institute of Electrical and Electronics Engineers, 2018. p. 672-675.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review
TY - GEN
T1 - A circuit-design-driven tool with a hybrid automation approach for SAR ADCs in IoT
AU - Ding,Ming
AU - Chen,Guibin
AU - Harpe,Pieter
AU - Busze,Benjamin
AU - Liu,Yao Hong
AU - Bachmann,Christian
AU - Philips,Kathleen
AU - van Roermund,Arthur
PY - 2018/4/19
Y1 - 2018/4/19
N2 - A circuit-design-driven tool with a hybrid design automation approach for asynchronous SAR ADCs in IoT applications is presented. To minimize the circuit design time while still being able to maintain ADC performance, the hybrid approach allocates automation and manual effort properly for each block: fully-synthesized control logic, highly-automated DAC and S&H circuit, library-based comparator and template-based layout generation. A user interface governs the automated design flow from specification and circuit implementation to layout generation. Two prototypes are generated using the proposed flow in 40nm CMOS: an 8b 32MS/s and a 12b 1MS/s SAR ADC. The measured and the simulated ADC performance are in good agreement, showing the robustness of the proposed method. At 1V supply, two chips consume 187μW and 16.7μW, achieving 30.7fJ/conversion.step and 18.1fJ/conversion.step respectively.
AB - A circuit-design-driven tool with a hybrid design automation approach for asynchronous SAR ADCs in IoT applications is presented. To minimize the circuit design time while still being able to maintain ADC performance, the hybrid approach allocates automation and manual effort properly for each block: fully-synthesized control logic, highly-automated DAC and S&H circuit, library-based comparator and template-based layout generation. A user interface governs the automated design flow from specification and circuit implementation to layout generation. Two prototypes are generated using the proposed flow in 40nm CMOS: an 8b 32MS/s and a 12b 1MS/s SAR ADC. The measured and the simulated ADC performance are in good agreement, showing the robustness of the proposed method. At 1V supply, two chips consume 187μW and 16.7μW, achieving 30.7fJ/conversion.step and 18.1fJ/conversion.step respectively.
KW - Design Automation
KW - Hybrid
KW - SAR ADC
UR - http://www.scopus.com/inward/record.url?scp=85048826219&partnerID=8YFLogxK
U2 - 10.23919/DATE.2018.8342094
DO - 10.23919/DATE.2018.8342094
M3 - Conference contribution
VL - 2018-January
SP - 672
EP - 675
BT - Proceedings of the 2018 Design, Automation and Test in Europe Conference and Exhibition, DATE 2018
PB - Institute of Electrical and Electronics Engineers
ER -