A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation.

S. Moreno Londono; J. Pineda de Gyvez

doi:10.1109/SOCC.2012.6398370

A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation.

S. Moreno Londono
, J. Pineda de Gyvez

Electronic Systems

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

5 Citations (Scopus)

Abstract

Digital circuits have been traditionally designed to meet the worst PVT conditions to guarantee high yield. This design methodology produces an integrated circuit which has a big overhead in terms of area and power consumption in most of the cases. In this paper, a new better-than-worst-case-design methodology is proposed. It is based on a timing error speculation technique which features simple monitors located in the critical paths of the circuit that will speculate whether a timing error is going to occur or not. Using a 32-bit multiplier, this design methodology achieved area and power savings up to 50%, with 5 % performance loss.

Original language	English
Title of host publication	Proceedings of the 25th IEEE Systems-on-Chip Conference, SOCC 2012, 12-14 september 2012, Niagara Falls, New York
Place of Publication	Piscataway
Publisher	Institute of Electrical and Electronics Engineers
Pages	15-20
ISBN (Print)	978-1-4673-1294-3
DOIs	https://doi.org/10.1109/SOCC.2012.6398370
Publication status	Published - 2012
Event	25th IEEE International Systems on Chip Conference, SOCC 2012 - Niagara Falls, United States Duration: 12 Sept 2012 → 14 Sept 2012 Conference number: 25

Conference

Conference	25th IEEE International Systems on Chip Conference, SOCC 2012
Abbreviated title	SOCC 2012
Country/Territory	United States
City	Niagara Falls
Period	12/09/12 → 14/09/12

Access to Document

10.1109/SOCC.2012.6398370

Cite this

Moreno Londono, S., & Pineda de Gyvez, J. (2012). A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation. In Proceedings of the 25th IEEE Systems-on-Chip Conference, SOCC 2012, 12-14 september 2012, Niagara Falls, New York (pp. 15-20). Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/SOCC.2012.6398370

@inproceedings{42a26b9b8dfa45f19d1990b403a90f19,

title = "A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation.",

abstract = "Digital circuits have been traditionally designed to meet the worst PVT conditions to guarantee high yield. This design methodology produces an integrated circuit which has a big overhead in terms of area and power consumption in most of the cases. In this paper, a new better-than-worst-case-design methodology is proposed. It is based on a timing error speculation technique which features simple monitors located in the critical paths of the circuit that will speculate whether a timing error is going to occur or not. Using a 32-bit multiplier, this design methodology achieved area and power savings up to 50\%, with 5 \% performance loss.",

author = "\{Moreno Londono\}, S. and \{Pineda de Gyvez\}, J.",

year = "2012",

doi = "10.1109/SOCC.2012.6398370",

language = "English",

isbn = "978-1-4673-1294-3",

pages = "15--20",

booktitle = "Proceedings of the 25th IEEE Systems-on-Chip Conference, SOCC 2012, 12-14 september 2012, Niagara Falls, New York",

publisher = "Institute of Electrical and Electronics Engineers",

address = "United States",

note = "25th IEEE International Systems on Chip Conference, SOCC 2012, SOCC 2012 ; Conference date: 12-09-2012 Through 14-09-2012",

}

Moreno Londono, S & Pineda de Gyvez, J 2012, A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation. in Proceedings of the 25th IEEE Systems-on-Chip Conference, SOCC 2012, 12-14 september 2012, Niagara Falls, New York. Institute of Electrical and Electronics Engineers, Piscataway, pp. 15-20, 25th IEEE International Systems on Chip Conference, SOCC 2012, Niagara Falls, New York, United States, 12/09/12. https://doi.org/10.1109/SOCC.2012.6398370

A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation. / Moreno Londono, S.; Pineda de Gyvez, J.
Proceedings of the 25th IEEE Systems-on-Chip Conference, SOCC 2012, 12-14 september 2012, Niagara Falls, New York. Piscataway: Institute of Electrical and Electronics Engineers, 2012. p. 15-20.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Academic › peer-review

TY - GEN

T1 - A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation.

AU - Moreno Londono, S.

AU - Pineda de Gyvez, J.

N1 - Conference code: 25

PY - 2012

Y1 - 2012

N2 - Digital circuits have been traditionally designed to meet the worst PVT conditions to guarantee high yield. This design methodology produces an integrated circuit which has a big overhead in terms of area and power consumption in most of the cases. In this paper, a new better-than-worst-case-design methodology is proposed. It is based on a timing error speculation technique which features simple monitors located in the critical paths of the circuit that will speculate whether a timing error is going to occur or not. Using a 32-bit multiplier, this design methodology achieved area and power savings up to 50%, with 5 % performance loss.

AB - Digital circuits have been traditionally designed to meet the worst PVT conditions to guarantee high yield. This design methodology produces an integrated circuit which has a big overhead in terms of area and power consumption in most of the cases. In this paper, a new better-than-worst-case-design methodology is proposed. It is based on a timing error speculation technique which features simple monitors located in the critical paths of the circuit that will speculate whether a timing error is going to occur or not. Using a 32-bit multiplier, this design methodology achieved area and power savings up to 50%, with 5 % performance loss.

U2 - 10.1109/SOCC.2012.6398370

DO - 10.1109/SOCC.2012.6398370

M3 - Conference contribution

SN - 978-1-4673-1294-3

SP - 15

EP - 20

BT - Proceedings of the 25th IEEE Systems-on-Chip Conference, SOCC 2012, 12-14 september 2012, Niagara Falls, New York

PB - Institute of Electrical and Electronics Engineers

CY - Piscataway

T2 - 25th IEEE International Systems on Chip Conference, SOCC 2012

Y2 - 12 September 2012 through 14 September 2012

ER -

Moreno Londono S, Pineda de Gyvez J. A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation. In Proceedings of the 25th IEEE Systems-on-Chip Conference, SOCC 2012, 12-14 september 2012, Niagara Falls, New York. Piscataway: Institute of Electrical and Electronics Engineers. 2012. p. 15-20 doi: 10.1109/SOCC.2012.6398370

A better-than-worst-case circuit design methodology using timing-error speculation and frequency adaptation.

Abstract

Conference

Access to Document

Fingerprint

Cite this